Mitsumasa Koyanagi

69 papers A* 1A 2C 1Journal 7Unranked 57

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	Die-Level Transformation From 2D Shuttle Chips to 3D-IC With TSV for Advanced Rapid Prototyping Methodology With Meta Bonding. IEEE J. Emerg. Sel. Topics Circuits Syst. Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2023	—	`conf`	Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding. 3DIC Mariappan Murugesan, Masahiro Sawa, E. Sone, Makoto Motoyoshi, Mitsumasa Koyanagi, Takafumi Fukushima
2023	—	`conf`	Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last. 3DIC Jiayi Shen, Chang Liu, Tadaaki Hoshi, Atsushi Shinoda, Hisashi Kino, Tetsu Tanaka, Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima
2021	—	`conf`	Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications. 3DIC Mariappan Murugesan, E. Sone, A. Simomura, Makoto Motoyoshi, Masahiro Sawa, K. Fukuda, Mitsumasa Koyanagi, Takafumi Fukushima
2021	—	`conf`	Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. 3DIC Koji Kiyoyama, Yoshihiko Horio, Takafumi Fukushima, Hiroyuki Hashimoto, Takemori Orima, Mitsumasa Koyanagi
2021	—	`conf`	Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. 3DIC Yoshihiko Horio, Takemori Orima, Koji Kiyoyama, Mitsumasa Koyanagi
2021	—	`conf`	Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. 3DIC Takafumi Fukushima, Shinichi Sakuyama, Masatomo Takahashi, Hiroyuki Hashimoto, Jichoel Bea, Theodorus Marcello, Hisashi Kino, Tetsu Tanaka, Mitsumasa Koyanagi, Mariappan Murugesan
2020	—	`conf`	3D Heterogeneous Integration Technology for AI System. VLSI-DAT Mitsumasa Koyanagi
2019	—	`conf`	Cu-Cu Bonding Challenges with 'i-ACF' for Advanced 3D Integration. 3DIC Shunji Kurooka, Yoshinori Hotta, Ai Nakamura, Mitsumasa Koyanagi, Takafumi Fukushima
2019	—	`conf`	Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. 3DIC Mariappan Murugesan, Mitsumasa Koyanagi, Hiroyuki Hashimoto, Ji Chel Bea, Takafumi Fukushima
2019	—	`conf`	Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI. 3DIC Mariappan Murugesan, Mitsumasa Koyanagi, Takafumi Fukushima
2016	—	`conf`	3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. 3DIC Makoto Motoyoshi, Kohki Yanagimura, Taikoh Fushimi, Junichi Takanohashi, Mariappan Murugesan, Masahiro Aoyagi, Mitsumasa Koyanagi
2016	—	`conf`	Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. 3DIC Mariappan Murugesan, Jichel Bea, Takafumi Fukushima, Makoto Motoyoshi, Tetsu Tanaka, Mitsumasa Koyanagi
2016	—	`conf`	Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. 3DIC Kang Wook Lee, Ai Nakamura, Jicheol Bea, Takafumi Fukushima, Suresh Ramalingam, Xin Wu, Tanaka Tanaka, Mitsumasa Koyanagi
2016	—	`conf`	New concept of TSV formation methodology using Directed Self-Assembly (DSA). 3DIC Takafumi Fukushima, Mariappan Murugesan, Shin Ohsaki, Hiroyuki Hashimoto, Jichoel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi
2016	J	`jnl`	Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. Micromachines Takafumi Fukushima, Hideto Hashiguchi, Hiroshi Yonekura, Hisashi Kino, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi
2015	—	`conf`	Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC. 3DIC Hisashi Kino, Hideto Hashiguchi, Seiya Tanikawa, Yohei Sugawara, Shunsuke Ikegaya, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka
2015	—	`conf`	Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. IRPS Kang Wook Lee, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2015	—	`conf`	Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors. 3DIC Seiya Tanikawa, Hisashi Kino, Takafumi Fukushima, Mitsumasa Koyanagi, Tetsu Tanaka
2015	J	`jnl`	Recent progress in 3D integration technology. IEICE Electron. Express Mitsumasa Koyanagi
2015	—	`conf`	Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers. 3DIC K. W. Lee, Chisato Nagai, Ai Nakamura, Hiroki Aizawa, Ji Chel Bea, Mitsumasa Koyanagi, Hideto Hashiguchi, Takafumi Fukushima, Tanaka Tanaka
2015	—	`conf`	Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. 3DIC Takafumi Fukushima, Taku Suzuki, Hideto Hashiguchi, Chisato Nagai, Jichoel Bea, Hiroyuki Hashimoto, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Kazushi Asami, Yasuhiro Kitamura, Mitsumasa Koyanagi
2015	—	`conf`	Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. 3DIC Yangyang Yan, Yingtao Ding, Qianwen Chen, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi
2014	—	`conf`	Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. 3DIC K. W. Lee, Chisato Nagai, Ai Nakamura, Ji Chel Bea, Mariappan Murugesan, Takafumi Fukushima, Tanaka Tanaka, Mitsumasa Koyanagi
2014	—	`conf`	Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. 3DIC Takafumi Fukushima, Yuka Ito, Mariappan Murugesan, Jicheol Bea, Kang Wook Lee, Koji Choki, Tetsu Tanaka, Mitsumasa Koyanagi
2013	—	`conf`	3D memory chip stacking by multi-layer self-assembly technology. 3DIC Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Ho-Young Son, Min-Suk Suh, K.-Y. Byun, N.-S. Kim, Kang Wook Lee, Mitsumasa Koyanagi
2013	—	`conf`	A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. 3DIC Kouji Kiyoyama, Y. Sato, Hiroyuki Hashimoto, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2013	—	`conf`	Development of via-last 3D integration technologies using a new temporary adhesive system. 3DIC Takafumi Fukushima, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Mitsumasa Koyanagi
2013	—	`conf`	Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. 3DIC Mariappan Murugesan, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi, Yuji Sutou, H. Wang, J. Koike
2013	—	`conf`	Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. 3DIC Hiroyuki Hashimoto, Takafumi Fukushima, Kang Wook Lee, Mitsumasa Koyanagi, Tetsu Tanaka
2013	—	`conf`	Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. 3DIC Kang Wook Lee, Seiya Tanikawa, Mariappan Murugesan, H. Naganuma, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2012	—	`ed.`	2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31 - February 2, 2012 3DIC Mitsumasa Koyanagi, Morihiro Kada
2012	—	`conf`	A 19nm 112.8mm ISSCC Noboru Shibata, Kazushige Kanda, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Kazuko Inuzuka, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, J. Nakai, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Makoto Miakashi, Naoki Kobayashi, M. Inagaki, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, D. He, Yasuhiko Honda, Junji Musha, Masaki Nakagawa, Mitsuaki Honma, Naofumi Abiko, Mitsumasa Koyanagi, Masahiro Yoshihara, Kazumi Ino, Mitsuhiro Noguchi, Teruhiko Kamei, Yosuke Kato, Shingo Zaitsu, Hiroaki Nasu, Takuya Ariki, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita, G. Liang, Gertjan Hemink, Farookh Moogat, Cuong Trinh, Masaaki Higashitani, Tuan Pham, Kousuke Kanazawa
2011	A	`conf`	3D super chip technology to achieve low-power and high-performance system-on-a chip. ISLPED Mitsumasa Koyanagi
2011	—	`conf`	A very low area ADC for 3-D stacked CMOS image processing system. 3DIC Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, H. Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi
2011	—	`conf`	Chip-level TSV integration for rapid prototyping of 3D system LSIs. 3DIC Kazuyuki Hozawa, Futoshi Furuta, Yuko Hanaoka, Mayu Aoki, Kenichi Takeda, Katsuyuki Sakuma, Kang Wook Lee, Takafumi Fukushima, Mitsumasa Koyanagi
2011	—	`conf`	Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. 3DIC Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2011	—	`conf`	High density Cu-TSVs and reliability issues. 3DIC Mariappan Murugesan, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2011	—	`conf`	High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. 3DIC Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Yuki Ohara, Tetsu Tanaka, Mitsumasa Koyanagi
2011	—	`conf`	High-bandwidth data transmission of new transceiver module through optical interconnection. 3DIC Yuka Ito, Shinsuke Terada, Shinya Arai, Koji Choki, Takafumi Fukushima, Mitsumasa Koyanagi
2011	—	`conf`	Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. 3DIC Yuki Ohara, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2011	J	`jnl`	Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. Micromachines Takafumi Fukushima, Takayuki Konno, Eiji Iwata, Risato Kobayashi, Toshiya Kojima, Mariappan Murugesan, Ji Chel Bea, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi
2011	—	`conf`	Stacked SOI pixel detector using versatile fine pitch μ-bump technology. 3DIC Makoto Motoyoshi, Junichi Takanohashi, Takafumi Fukushima, Yasuo Arai, Mitsumasa Koyanagi
2011	—	`conf`	Temporary bonding strength control for self-assembly-based 3D integration. 3DIC Takafumi Fukushima, Yuki Ohara, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi
2011	—	`conf`	W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress. 3DIC Mariappan Murugesan, Hideto Hashiguchi, Harufumi Kobayashi, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2010	—	`conf`	A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. 3DIC Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima, H. Naganuma, Hiroaki Kobayashi, Tetsu Tanaka, Mitsumasa Koyanagi
2010	—	`conf`	Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 3DIC Takafumi Fukushima, Eiji Iwata, Jichoel Bea, Mariappan Murugesan, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi
2010	—	`conf`	Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 3DIC Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2010	—	`conf`	Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. CICC Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka
2010	—	`conf`	Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. 3DIC Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2009	—	`conf`	10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. 3DIC Yuki Ohara, Akihiro Noriki, Katsuyuki Sakuma, Kang Wook Lee, Mariappan Murugesan, Jichoel Bea, Fumiaki Yamada, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2009	—	`conf`	3D integration technology for 3D stacked retinal chip. 3DIC Yoshiyuki Kaiho, Yuki Ohara, Hirotaka Takeshita, Kouji Kiyoyama, Kang Wook Lee, Tetsu Tanaka, Mitsumasa Koyanagi
2009	—	`conf`	A parallel ADC for high-speed CMOS image processing system with 3D structure. 3DIC Kouji Kiyoyama, Yuki Ohara, Kang Wook Lee, Y. Yang, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2009	—	`conf`	Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. 3DIC Takafumi Fukushima, Eiji Iwata, Tetsu Tanaka, Mitsumasa Koyanagi
2009	—	`conf`	Heterogeneous integration technology for MEMS-LSI multi-chip module. 3DIC Kang Wook Lee, Shigeyuki Kanno, Yuki Ohara, Kouji Kiyoyama, Ji Chel Bea, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2009	J	`jnl`	High-Density Through Silicon Vias for 3-D LSIs. Proc. IEEE Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka
2009	—	`conf`	Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. 3DIC Ji Chel Bea, Mariappan Murugesan, Yuki Ohara, Akihiro Noriki, Hisashi Kino, Kang Wook Lee, Takafumi Fukushima, Tetsu Tanaka, Mitsumasa Koyanagi
2009	—	`conf`	Three-dimensional integration technology and integrated systems. ASP-DAC Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka
2006	A	`conf`	Development of a High Speed Vision System for Mobile Robots. IROS Atsushi Konno, Ryo Uchikura, Toshiyuki Ishihara, Teppei Tsujita, Takeaki Sugimura, Jun Deguchi, Mitsumasa Koyanagi, Masaru Uchiyama
2005	—	`conf`	Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. ARCS Workshops Takeaki Sugimura, Yuta Konishi, Yoshihiro Nakatani, Takafumi Fukushima, Hiroyuki Kurino, Mitsumasa Koyanagi
2004	C	`conf`	Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. PDCAT Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
2004	—	`conf`	Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. AINA (2) Zhe Liu, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
2003	—	`conf`	Parallel image processing field programmable gate array for real time image processing system. FPT Takeaki Sugimura, JeoungChill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi
2002	A*	`conf`	Nanometer design: what hurts next...? DAC Robert W. Brodersen, Anthony M. Hill, John Kibarian, Desmond Kirkpatrick, Mark A. Lavin, Mitsumasa Koyanagi
2000	—	`conf`	Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. NIPS Hiroyuki Kurino, Masaki Nakagawa, Kang Wook Lee, Tomonori Nakamura, Yuusuke Yamada, Ki Tae Park, Mitsumasa Koyanagi
1998	—	`conf`	A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. ASP-DAC Keiichi Hirano, Taizou Ono, Hiroyuki Kurino, Mitsumasa Koyanagi
1998	J	`jnl`	Future system-on-silicon LSI chips. IEEE Micro Mitsumasa Koyanagi, Hiroyuki Kurino, Kang Wook Lee, Katsuyuki Sakuma, Nobuaki Miyakawa, Hikotaro Itani
1991	—	`conf`	A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. VLSI Mitsumasa Koyanagi
1990	J	`jnl`	Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system. IEEE J. Solid State Circuits Mitsumasa Koyanagi, Hidehiro Takata, Hiroki Mori, Junichiro Iba