Mitsuji Okada

12 papers C 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2023 J jnl
A 7-nm FinFET 1.2-TB/s/mm
IEEE J. Solid State Circuits
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2023 J jnl
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022 — conf
A 7-nm FinFET 1.2-TB/s/mm
HCS
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2022 — conf
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format.
NEWCAS
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
2019 C conf
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming.
ISCAS
Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda
2015 J jnl
An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2015 J jnl
Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation.
IEICE Electron. Express
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2014 — conf
A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis.
NEWCAS
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2012 J jnl
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique.
IEEE J. Solid State Circuits
Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno
2010 J jnl
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter.
IEEE J. Solid State Circuits
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
2010 — conf
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC.
ISSCC
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
2000 — conf
A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home.
CICC
Shinichi Kozu, Toshiya Aramaki, Chinatsu Ikeda, Yasuaki Kuroda, Satoru Kawanago, Mitsuji Okada, Hiroshi Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii