Mitra Mirhassani

73 papers B 4C 13Misc 1Journal 33Unranked 22
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform.
CoRR
Moslem Heidarpur, Mitra Mirhassani, Norman Chang
2025 — conf
A Novel and Efficient Large Integer Number Theoretic Transform Multiplier Based on Unified Blocks.
LASCAS
Shiva Nejati, Moslem Heidarpur, Mitra Mirhassani
2025 J jnl
A comprehensive review of security vulnerabilities in heavy-duty vehicles: Comparative insights and current research gaps.
Comput. Secur.
Narges Rahimi, Beth-Anne Schuelke Leech, Mitra Mirhassani
2025 J jnl
Enhanced TARA model for heavy-duty vehicles using ISO/SAE 21434 and Fuzzy Analytic Hierarchy Process (FAHP).
Expert Syst. Appl.
Narges Rahimi, Beth-Anne Schuelke Leech, Mitra Mirhassani
2025 J jnl
Harnessing Fuzzing Capabilities to Improve Automotive Cybersecurity.
IEEE Access
Kunj Dhonde, Ikjot Saini, Mitra Mirhassani
2025 B conf
Mitigating Adversarial Attacks in Object Detection using Multi-Modal Fusion in Autonomous Vehicles.
MASS
Ifrah Andleeb, Arsalan Hameed, Katsuya Suto, Mitra Mirhassani, Ning Zhang
2025 — conf
ScoreCAM and Segmentation-Based Adversarial Attacks in Autonomous Vehicles.
VTC2025-Fall
Ifrah Andleeb, Katsuya Suto, Mitra Mirhassani, Ning Zhang
2025 — conf
System Engineering-Based Threat Modeling for Heavy-Duty Vehicles.
SysCon
Narges Rahimi, Beth-Anne Schuelke Leech, Mitra Mirhassani
2025 — conf
Toward Full GPU Acceleration of Agile Homomorphic Encryption Frameworks.
LASCAS
Emilio Quaggiotto, Shiva Nejati, Alexander J. Leigh, Mitra Mirhassani
2024 J jnl
A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2
IEEE Trans. Very Large Scale Integr. Syst.
Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid
2024 J jnl
Cyber Resiliency Enhancement of Overcurrent Relays in Distribution Systems.
IEEE Trans. Smart Grid
Saad Pola, Marko Jovanovic, Maher A. Azzouz, Mitra Mirhassani
2023 J jnl
A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron.
IEEE Trans. Very Large Scale Integr. Syst.
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
2023 J jnl
Developing a fuzzy optimized model for selecting a maintenance strategy in the paper industry: An integrated FGP-ANP-FMEA approach.
Expert Syst. Appl.
Foroogh Behnia, Habib Zare Ahmadabadi, Beth-Anne Schuelke Leech, Mitra Mirhassani
2023 J jnl
Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments.
IEEE Trans. Circuits Syst. II Express Briefs
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
2023 C conf
High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons.
ISCAS
Edris Zaman Farsa, Moslem Heidarpur, Arash Ahmadi, Mitra Mirhassani
2023 J jnl
Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations.
IEEE Trans. Very Large Scale Integr. Syst.
Madhan Thirumoorthi, Alexander J. Leigh, Moslem Heidarpur, Mohammed A. S. Khalid, Mitra Mirhassani
2022 J jnl
A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters.
IEEE Trans. Circuits Syst. II Express Briefs
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
2022 — conf
A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron.
PRIME
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
2022 J jnl
A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach.
IEEE Trans. Very Large Scale Integr. Syst.
Hamidreza Esmaeili Taheri, Mitra Mirhassani
2022 J jnl
An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst.
Madhan Thirumoorthi, Moslem Heidarpur, Mitra Mirhassani, Mohammed A. S. Khalid
2022 J jnl
Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation".
IEEE Trans. Very Large Scale Integr. Syst.
Moslem Heidarpur, Mitra Mirhassani
2022 C conf
Selective Input Sparsity in Spiking Neural Networks for Pattern Classification.
ISCAS
Alexander J. Leigh, Moslem Heidarpur, Mitra Mirhassani
2021 J jnl
An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation.
IEEE Trans. Very Large Scale Integr. Syst.
Moslem Heidarpur, Mitra Mirhassani
2021 J jnl
Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF.
IEEE Trans. Very Large Scale Integr. Syst.
Madhan Thirumoorthi, Marko Jovanovic, Mitra Mirhassani, Mohammed A. S. Khalid
2021 J jnl
Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference.
Microelectron. J.
Neda Rezaei, Mitra Mirhassani
2020 C conf
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model.
ISCAS
Alexander J. Leigh, Mitra Mirhassani, Roberto Muscedere
2020 J jnl
An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model.
IEEE Trans. Circuits Syst.
Alexander J. Leigh, Mitra Mirhassani, Roberto Muscedere
2019 J jnl
A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar.
IEEE Trans. Very Large Scale Integr. Syst.
Iman Y. Taha, Mitra Mirhassani
2019 J jnl
A Varactor-Less DCO With 7GHz Tuning Range for 77GHz Automotive Radars.
IEEE Access
Iman Y. Taha, Mitra Mirhassani
2019 J jnl
Tunable Neuron With PWL Approximation Based on the Minimum Operator.
IEEE Trans. Circuits Syst. II Express Briefs
Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu
2018 — conf
A Monotonically Linear DCO for 77 GHz Automotive Radars.
MWSCAS
Iman Y. Taha, Mitra Mirhassani, Arezoo Emadi
2018 C conf
Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays.
ISCAS
Bahar Youssefi, Alexander J. Leigh, Mitra Mirhassani, Q. M. Jonathan Wu
2018 — conf
Review of Arithmetic Operations Using the Continuous Valued Number System.
MWSCAS
Babak Zamanlooy, Mitra Mirhassani, Majid Ahmadi
2017 — conf
A CMOS differential DCO with amplitude stabilization for 24GHz automotive radars.
CCECE
Iman Y. Taha, Mitra Mirhassani
2017 — conf
A neural network architecture using high resolution multiplying digital to analog converters.
MWSCAS
Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi
2017 — conf
A software tool for generating optimized multipartite table parameters.
CCECE
Roberto Muscedere, Mitra Mirhassani
2017 J jnl
An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips.
IEEE Trans. Very Large Scale Integr. Syst.
Babak Zamanlooy, Mitra Mirhassani
2017 — conf
An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition.
CCECE
Yuan Jing, Bahar Youssefi, Mitra Mirhassani, Roberto Muscedere
2017 J jnl
Mixed-signal VLSI neural network based on Continuous Valued Number System.
Neurocomputing
Babak Zamanlooy, Mitra Mirhassani
2017 J jnl
Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amps.
IET Circuits Devices Syst.
Seyed Mahmoud Anisheh, Hossein Shamsi, Mitra Mirhassani
2017 — conf
Two-electrode ECG measurement circuit using a feed forward CMRR enhancement method.
CCECE
Esrafil Jedari, Rashid Rashidzadeh, Mitra Mirhassani, Majid Ahmadi
2016 C conf
A 24GHz Digitally Controlled Oscillator for automotive radar in 65nm CMOS.
ISCAS
Iman Y. Taha, Mitra Mirhassani
2016 B conf
A digital neuromorphic circuit for neural-glial interaction.
IJCNN
Shaghayegh Gomar, Mitra Mirhassani, Majid Ahmadi, Mehrdad Saif
2016 C conf
Analog cellular neural network for application in physical unclonable functions.
ISCAS
Hadis Takaloo, Arash Ahmadi, Mitra Mirhassani, Majid Ahmadi
2016 — conf
Efficient mixed-signal synapse multipliers for multi-layer feed-forward neural networks.
MWSCAS
Bahar Youssefi, Mitra Mirhassani, Q. M. Jonathan Wu
2016 Misc conf
Precise digital implementations of hyperbolic tanh and sigmoid function.
ACSSC
Shaghayegh Gomar, Mitra Mirhassani, Majid Ahmadi
2015 B conf
A modular mixed-signal CVNS neural network architecture.
IJCNN
Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi
2015 J jnl
CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning.
IEEE Trans. Very Large Scale Integr. Syst.
Babak Zamanlooy, Mitra Mirhassani
2014 — conf
A low cost biomimetic implementation of a CPG based on AdEx neuron model.
ICECS
Shaghayegh Gomar, Arash Ahmadi, Shahpour Alirezaee, Majid Ahmadi, Mitra Mirhassani
2014 — conf
A temperature compensated relaxation oscillator for SoC implementations.
NEWCAS
Iman Y. Taha, Mitra Mirhassani
2014 C conf
Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System.
ISCAS
Babak Zamanlooy, Mitra Mirhassani
2014 J jnl
Area-efficient robust Madaline based on continuous valued number system.
Neurocomputing
Babak Zamanlooy, Mitra Mirhassani
2014 J jnl
Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function.
IEEE Trans. Very Large Scale Integr. Syst.
Babak Zamanlooy, Mitra Mirhassani
2012 — conf
A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks.
ISMVL
Farinoush Saffar, Mitra Mirhassani, Majid Ahmadi
2012 J jnl
A Prototype CVNS Distributed Neural Network Using Synapse-Neuron Modules.
IEEE Trans. Circuits Syst. I Regul. Pap.
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
2012 J jnl
Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron.
IEEE Trans. Very Large Scale Integr. Syst.
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
2012 — conf
Complexity Study of the Continuous Valued Number System Adders.
ISMVL
Babak Zamanlooy, Ashley Novak, Mitra Mirhassani
2012 C conf
Current mode multiple-valued adder for cryptography processors.
ISCAS
Ashley Novak, Farinoush Saffar, Mitra Mirhassani, Huapeng Wu
2012 — conf
Efficient hardware implementation of threshold neural networks.
NEWCAS
Babak Zamanlooy, Mitra Mirhassani
2011 C conf
A study on resistive-type truncated CVNS Distributed Neural Networks.
ISCAS
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
2011 J jnl
CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory.
IEEE Trans. Very Large Scale Integr. Syst.
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
2011 J jnl
Error Recovery in Continuous Valued Number System.
J. Circuits Syst. Comput.
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
2010 J jnl
Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio.
IEEE Trans. Circuits Syst. II Express Briefs
Golnar Khodabandehloo, Mitra Mirhassani, Majid Ahmadi
2010 C conf
System-level design of low complexity CVNS feed forward neural network.
ISCAS
Mitra Mirhassani, Babak Zamanlooy
2009 — conf
16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin.
ISMVL
Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi
2009 — conf
An area-speed efficient method for current mode analog to digital converters.
ECCTD
Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi
2009 C conf
Current-mode Multiple-valued Dynamic Memory.
ISCAS
Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi
2009 — conf
Mixed-signal CVNS adder for two-operand binary addition.
EIT
Mitra Mirhassani
2008 J jnl
Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing.
IEEE Trans. Very Large Scale Integr. Syst.
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
2008 C conf
Robust analog neural network based on continuous valued number system.
ISCAS
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
2007 C conf
Digital Multiplication using Continuous Valued Digits.
ISCAS
Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien
2004 B conf
A new mixed-signal feed-forward neural network with on-chip learning.
IJCNN
Mitra Mirhassani, Majid Ahmadi, William C. Miller
2003 — conf
A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays.
VLSI
Mitra Mirhassani, Majid Ahmadi, William C. Miller