Mirjana Stojilovic

46 papers A 17B 5C 1Misc 2Journal 13Unranked 7

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Out with LSQs: Custom Circuits for Memory Access Reordering in Dynamic HLS. FPGA Rouzbeh Pirayadi, Ayatallah Elakhras, Mirjana Stojilovic, Paolo Ienne
2025	—	`ed.`	Applied Reconfigurable Computing. Architectures, Tools, and Applications - 21st International Symposium, ARC 2025, Seville, Spain, April 9-11, 2025, Proceedings ARC Roberto Giorgi, Mirjana Stojilovic, Dirk Stroobandt, Piedad Brox Jiménez, Angel Barriga Barros
2025	A	`conf`	FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs. ICCAD Louis Coulon, Adham Ragab, Jason Anderson, Mirjana Stojilovic, Paolo Ienne
2025	A	`conf`	FRIDA: Reconfigurable Arrays for Dynamically Scheduled High-Level Synthesis. FPGA Louis Coulon, Lucas Ramirez, Jason Helge Anderson, Mirjana Stojilovic, Paolo Ienne
2025	Misc	`conf`	Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. FCCM Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2025	—	`conf`	ROBoost: A Study of FPGA Logic-Based Power-Wasting Primitives. ARC Dina G. Mahmoud, Simone Andreani, Vincent Lenders, Mirjana Stojilovic
2024	—	`conf`	Multiqueue-Based FPGA Routing: Relaxed A* Priority Ordering for Improved Parallelism. ICFPT Alexandre Singer, Hang Yan, Guozheng Zhang, Mark C. Jeffrey, Mirjana Stojilovic, Vaughn Betz
2024	—	`conf`	Parallel FPGA Routing with On-The-Fly Net Decomposition. ICFPT Fahrican Kosar, Mirjana Stojilovic, Vaughn Betz
2024	J	`jnl`	X-Attack 2.0: The Risk of Power Wasters and Satisfiability Don't-Care Hardware Trojans to Shared Cloud FPGAs. IEEE Access Dina G. Mahmoud, Beatrice Shokry, Vincent Lenders, Wei Hu, Mirjana Stojilovic
2023	J	`jnl`	A Visionary Look at the Security of Reconfigurable Cloud Computing. Proc. IEEE Mirjana Stojilovic, Kasper Rasmussen, Francesco Regazzoni, Mehdi B. Tahoori, Russell Tessier
2023	C	`conf`	Active Wire Fences for Multitenant FPGAs. DDECS Ognjen Glamocanin, Andela Kostic, Stasa Kostic, Mirjana Stojilovic
2023	J	`jnl`	Electrical-Level Attacks on CPUs, FPGAs, and GPUs: Survey and Implications in the Heterogeneous Era. ACM Comput. Surv. Dina G. Mahmoud, Vincent Lenders, Mirjana Stojilovic
2023	B	`conf`	GRAMM: Fast CGRA Application Mapping Based on A Heuristic for Finding Graph Minors. FPL Guanglei Zhou, Mirjana Stojilovic, Jason Helge Anderson
2023	A	`conf`	IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	J	`jnl`	Instruction-Level Power Side-Channel Leakage Evaluation of Soft-Core CPUs on Shared FPGAs. J. Hardw. Syst. Secur. Ognjen Glamocanin, Shashwat Shrivastava, Jinwei Yao, Nour Ardo, Mathias Payer, Mirjana Stojilovic
2023	A	`conf`	Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic
2023	J	`jnl`	RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. IACR Cryptol. ePrint Arch. David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic
2023	J	`jnl`	RDS: FPGA Routing Delay Sensors for Effective Remote Power Analysis Attacks. IACR Trans. Cryptogr. Hardw. Embed. Syst. David Spielmann, Ognjen Glamocanin, Mirjana Stojilovic
2023	A	`conf`	Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAs. DATE Ognjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic
2023	J	`jnl`	The Side-channel Metrics Cheat Sheet. ACM Comput. Surv. Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic
2022	A	`conf`	A Deep-Learning Approach to Side-Channel Based CPU Disassembly at Design Time. DATE Hedi Fendri, Marco Macchetti, Jérôme Perrine, Mirjana Stojilovic
2022	J	`jnl`	DFAulted: Analyzing and Exploiting CPU Software Faults Caused by FPGA-Driven Undervolting Attacks. IEEE Access Dina G. Mahmoud, David Dervishi, Samah Hussein, Vincent Lenders, Mirjana Stojilovic
2022	A	`conf`	FPGA-to-CPU Undervolting Attacks. DATE Dina G. Mahmoud, Samah Hussein, Vincent Lenders, Mirjana Stojilovic
2022	J	`jnl`	The Side-Channel Metric Cheat Sheet. IACR Cryptol. ePrint Arch. Kostas Papagiannopoulos, Ognjen Glamocanin, Melissa Azouaoui, Dorian Ros, Francesco Regazzoni, Mirjana Stojilovic
2021	—	`conf`	Deep Learning Detection of GPS Spoofing. LOD Olivia Jullian, Beatriz Otero, Mirjana Stojilovic, Juan José Costa, Javier Verdú, Manuel Alejandro Pajuelo
2021	A	`conf`	NetCracker: A Peek into the Routing Architecture of Xilinx 7-Series FPGAs. FPGA Morten B. Petersen, Stefan Nikolic, Mirjana Stojilovic
2021	A	`conf`	Shared FPGAs and the Holy Grail: Protections against Side-Channel and Fault Attacks. DATE Ognjen Glamocanin, Dina G. Mahmoud, Francesco Regazzoni, Mirjana Stojilovic
2021	J	`jnl`	Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing. IEEE Access Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
2020	Misc	`conf`	A Shared-Memory Parallel Implementation of the RePlAce Global Cell Placer. VLSID Frédéric Gessler, Philip Brisk, Mirjana Stojilovic
2020	A	`conf`	Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks? DATE Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic
2020	A	`conf`	Built-in Self-Evaluation of First-Order Power Side-Channel Leakage for FPGAs. FPGA Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni, Mirjana Stojilovic
2020	A	`conf`	Closing Leaks: Routing Against Crosstalk Side-Channel Attacks. FPGA Zeinab Seifoori, Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
2020	A	`conf`	CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. FPGA Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic
2020	J	`jnl`	CloudMoles: Surveillance of Power-Wasting Activities by Infiltrating Undercover Sensors. IACR Cryptol. ePrint Arch. Seyedeh Sharareh Mirzargar, Andrea Guerrieri, Mirjana Stojilovic
2020	—	`conf`	Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. FPT Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic
2020	J	`jnl`	Nonintrusive and Adaptive Monitoring for Locating Voltage Attacks in Virtualized FPGAs. IACR Cryptol. ePrint Arch. Seyedeh Sharareh Mirzargar, Gaiëtan Renault, Andrea Guerrieri, Mirjana Stojilovic
2020	B	`conf`	X-Attack: Remote Activation of Satisfiability Don't-Care Hardware Trojans on Shared FPGAs. FPL Dina G. Mahmoud, Wei Hu, Mirjana Stojilovic
2019	—	`conf`	A Machine Learning Approach for Power Gating the FPGA Routing Network. FPT Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic
2019	A	`conf`	Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform. FPGA Dario Korolija, Mirjana Stojilovic
2019	—	`conf`	FPGA-Assisted Deterministic Routing for FPGAs. IPDPS Workshops Dario Korolija, Mirjana Stojilovic
2019	B	`conf`	Physical Side-Channel Attacks and Covert Communication on FPGAs: A Survey. FPL Seyedeh Sharareh Mirzargar, Mirjana Stojilovic
2019	A	`conf`	Timing Violation Induced Faults in Multi-Tenant FPGAs. DATE Dina Mahmoud, Mirjana Stojilovic
2018	B	`conf`	Deterministic Parallel Routing for FPGAs Based on Galois Parallel Execution Model. FPL Yehdhih Ould Mohammed Moctar, Mirjana Stojilovic, Philip Brisk
2017	B	`conf`	Parallel FPGA routing: Survey and challenges. FPL Mirjana Stojilovic
2013	J	`jnl`	Selective Flexibility: Creating Domain-Specific Reconfigurable Arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne
2012	A	`conf`	Selective flexibility: Breaking the rigidity of datapath merging. DATE Mirjana Stojilovic, David Novo, Lazar Saranovac, Philip Brisk, Paolo Ienne