Miriam Leeser - RankMe

196 papers A* 6A 19B 9C 12Misc 15Journal 64Unranked 66

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Survey of FPGA-based 3D CNN Accelerators and Hardware-aware Algorithmic Optimizations. ACM Comput. Surv. Dana Diaconu, Xue Lin, Michaela Blott, Miriam Leeser
2025	—	`conf`	LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference. ASP-DAC Yanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin
2025	J	`jnl`	Memory-efficient Sketch Acceleration for Handling Large Network Flows on FPGAs. CoRR Zhaoyang Han, Yicheng Qian, Michael Zink, Miriam Leeser
2025	—	`conf`	Miniature: Fast AI Supercomputer Networks Simulation on FPGAs. APNet Yicheng Qian, Ran Shu, Rui Ma, Yang Wang, Derek Chiou, Nadeen Gebara, Luca Piccolboni, Miriam Leeser, Yongqiang Xiong
2025	—	`conf`	TerraSense: FPGA Accelerated Vision-based Terrain Classification for Autonomous Robot Navigation. ICAR Maria Gianello, Dana Diaconu, Miriam Leeser
2025	Misc	`conf`	Transfer Learning on the Edge for a Wireless Application Using an SoC Platform. FCCM Yiyue Jiang, John Dooley, Aidan Edward Colgan, Jonathan Guimaraes Ribeiro, Zhilin Ren, Miriam Leeser
2024	J	`jnl`	EdgeQAT: Entropy and Distribution Guided Quantization-Aware Training for the Acceleration of Lightweight LLMs on the Edge. CoRR Xuan Shen, Zhenglun Kong, Changdi Yang, Zhaoyang Han, Lei Lu, Peiyan Dong, Cheng Lyu, Chih-hsiang Li, Xuehang Guo, Zhihao Shu, Wei Niu, Miriam Leeser, Pu Zhao, Yanzhi Wang
2024	A	`conf`	Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. FPGA Yiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser
2024	J	`jnl`	Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. Sensors Yiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser
2024	—	`conf`	Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge. HPEC Zhaoyang Han, Andrew Briasco-Stewart, Michael Zink, Miriam Leeser
2024	J	`jnl`	Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge. CoRR Zhaoyang Han, Andrew Briasco-Stewart, Michael Zink, Miriam Leeser
2024	J	`jnl`	LUTMUL: Exceed Conventional FPGA Roofline Limit by LUT-based Efficient Multiplication for Neural Network Inference. CoRR Yanyue Xie, Zhengang Li, Dana Diaconu, Suranga Handagala, Miriam Leeser, Xue Lin
2024	—	`conf`	Memory-Efficient Sketch Acceleration for Handling Large Network Flows on FPGAs. ICFPT Zhaoyang Han, Yicheng Qian, Michael Zink, Miriam Leeser
2024	—	`conf`	Optimizing FPGA Memory Allocation for Matrix-Matrix Multiplication Using Bayesian Optimization. HPEC Mehmet Güngör, Stratis Ioannidis, Miriam Leeser
2024	—	`conf`	P4-Based In-Network Telemetry for FPGAs in the Open Cloud Testbed and FABRIC. INFOCOM (Workshops) Sandeep Bal, Zhaoyang Han, Suranga Handagala, Mert Cevik, Michael Zink, Miriam Leeser
2024	C	`conf`	Quadrupedal Locomotion Control On Inclined Surfaces Using Collocation Method. ACC Adarsh Salagame, Maria Gianello, Chenghao Wang, Kaushik Venkatesh Krishnamurthy, Shreyansh Pitroda, Rohit Rajput, Eric Sihite, Miriam Leeser, Alireza Ramezani
2024	J	`jnl`	Realizing Network-Attached FPGAs in the Cloud. Comput. Sci. Eng. Miriam Leeser, Suranga Handagala, Dana Diaconu, Zhaoyang Han, Michael Zink
2024	—	`conf`	Ultra Low Latency Hardware Optimised Radix-4 FFT for Optical Wireless FPGA Transceivers Via Hermitian Symmetry Characteristics. HPEC Michael Codd, Ciara McDonald, Yiyue Jiang, Chunan Chen, Holger Claussen, Miriam Leeser, John Dooley
2023	—	`conf`	A Framework to Enable Runtime Programmable P4-enabled FPGAs in the Open Cloud Testbed. INFOCOM Workshops Zhaoyang Han, Suranga Handagala, Kalyani Patle, Michael Zink, Miriam Leeser
2023	—	`conf`	Accelerating Garbled Circuits in the Open Cloud Testbed with Multiple Network-Attached FPGAs. HPEC Kai Huang, Mehmet Güngör, Suranga Handagala, Stratis Ioannidis, Miriam Leeser
2023	J	`jnl`	Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track. ACM Trans. Reconfigurable Technol. Syst. Miriam Leeser
2023	—	`conf`	Machine Learning Across Network-Connected FPGAs. HPEC Dana Diaconu, Yanyue Xie, Mehmet Güngör, Suranga Handagala, Xue Lin, Miriam Leeser
2023	A	`conf`	Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems. DATE Yiyue Jiang, Andrius Vaicaitis, Miriam Leeser, John Dooley
2023	J	`jnl`	Quadrupedal Locomotion Control On Inclined Surfaces Using Collocation Method. CoRR Adarsh Salagame, Maria Gianello, Chenghao Wang, Kaushik Venkatesh Krishnamurthy, Shreyansh Pitroda, Rohit Rajput, Eric Sihite, Miriam Leeser, Alireza Ramezani
2023	—	`conf`	Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware. HPEC Justin Kawakami, Dominik Zajac, Miriam Leeser
2022	B	`conf`	Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. FPL Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang
2022	J	`jnl`	Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. CoRR Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang
2022	J	`jnl`	Evaluating Theoretical Baselines for ML Benchmarking Across Different Accelerators. IEEE Des. Test Michaela Blott, Alina Vasilciuc, Miriam Leeser, Linda Doyle
2022	A*	`conf`	FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results. DAC Mengshu Sun, Zhengang Li, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang
2022	—	`conf`	Hardware Software Codesign of Applications on the Edge: Accelerating Digital PreDistortion for Wireless Communications. HPEC Zhaoyang Han, Yiyue Jiang, Rahul Mushini, John Dooley, Miriam Leeser
2022	—	`conf`	Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations. IPDPS Workshops Dana Diaconu, Lucian Petrica, Michaela Blott, Miriam Leeser
2022	—	`conf`	Network Attached FPGAs in the Open Cloud Testbed (OCT). INFOCOM Workshops Suranga Handagala, Miriam Leeser, Kalyani Patle, Michael Zink
2022	—	`conf`	Optimizing Designs Using Several Types of Memories on Modern FPGAs. HPEC Mehmet Güngör, Kai Huang, Stratis Ioannidis, Miriam Leeser
2022	J	`jnl`	The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier
2021	—	`conf`	Accelerating Matrix Processing for MIMO Systems. HEART Jieming Xu, Miriam Leeser
2021	—	`conf`	Computationally Efficient Look-up-Tables for Behavioral Modelling and Digital Pre-distortion of Multi-standard Wireless Systems. CrownCom/WiCON Zhaoyang Han, Méabh Loughman, Yiyue Jiang, Rahul Mushini, Miriam Leeser, John Dooley
2021	J	`jnl`	Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach. IEEE Trans. Computers Michaela Blott, Nicholas J. Fraser, Giulio Gambardella, Lisa Halder, Johannes Kath, Zachary Neveu, Yaman Umuroglu, Alina Vasilciuc, Miriam Leeser, Linda Doyle
2021	J	`jnl`	FPGAs in the Cloud. Comput. Sci. Eng. Miriam Leeser, Suranga Handagala, Michael Zink, Volodymyr V. Kindratenko, Anne C. Elster
2021	—	`conf`	The Open Cloud Testbed (OCT): A Platform for Research into new Cloud Technologies. CloudNet Michael Zink, David Irwin, Emmanuel Cecchet, Hakan Saplakoglu, Orran Krieger, Martin C. Herbordt, Michael Daitzman, Peter Desnoyers, Miriam Leeser, Suranga Handagala
2020	A*	`conf`	3D CNN Acceleration on FPGA using Hardware-Aware Pruning. DAC Mengshu Sun, Pu Zhao, Mehmet Güngör, Massoud Pedram, Miriam Leeser, Xue Lin
2020	J	`jnl`	A Novel Physical Layer Authentication With PAPR Reduction Based on Channel and Hardware Frequency Responses. IEEE Trans. Circuits Syst. I Regul. Pap. Prasidh Ramabadran, Pavel Afanasyev, David Malone, Miriam Leeser, Darragh McCarthy, Bill O'Brien, Ronan Farrell, John Dooley
2020	—	`conf`	Demonstrating Spectrally Efficient Asynchronous Coexistence for Machine Type Communication: A Software Defined Radio Approach. CrownCom Suranga Handagala, Miriam Leeser
2020	A	`conf`	Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. FPGA Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle
2020	—	`conf`	Exploiting GPU Direct Access to Non-Volatile Memory to Accelerate Big Data Processing. HPEC Mahsa Bayati, Miriam Leeser, Ningfang Mi
2020	J	`jnl`	High-performance transformation of protein structure representation from internal to Cartesian coordinates. J. Comput. Chem. Mahsa Bayati, Miriam Leeser, Jaydeep P. Bardhan
2020	—	`conf`	Optimizing Use of Different Types of Memory for FPGAs in High Performance Computing. HPEC Kai Huang, Mehmet Güngör, Stratis Ioannidis, Miriam Leeser
2020	J	`jnl`	Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments. IEEE Access Suranga Handagala, Miriam Leeser
2020	J	`jnl`	Strategies and Demonstration to Support Multiple Wireless Protocols with a Single RF Front-End. IEEE Wirel. Commun. Mohamed Mohamed, Suranga Handagala, Jieming Xu, Miriam Leeser, Marvin Onabajo
2019	—	`conf`	Accelerating Large Garbled Circuits on an FPGA-enabled Cloud. H2RC@SC Miriam Leeser, Mehmet Güngör, Kai Huang, Stratis Ioannidis
2019	—	`conf`	An FPGA Design Technique to Receive Multiple Wireless Protocols with the Same RF Front End. Wireless Days Miriam Leeser, Suranga Handagala, Mohamed Mohamed, Jieming Xu, Marvin Onabajo
2019	—	`conf`	Garbled Circuits in the Cloud using FPGA Enabled Nodes. HPEC Kai Huang, Mehmet Güngör, Xin Fang, Stratis Ioannidis, Miriam Leeser
2019	J	`jnl`	Identifying volatile numeric expressions in numeric computing applications. Math. Comput. Simul. Mahsa Bayati, Miriam Leeser, Yijia Gu, Thomas Wahl
2019	J	`jnl`	New Performance Modeling Methods for Parallel Data Processing Applications. ACM Trans. Model. Comput. Simul. Janki Bhimani, Ningfang Mi, Miriam Leeser, Zhengyu Yang
2019	J	`jnl`	QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. CoRR Michaela Blott, Lisa Halder, Miriam Leeser, Linda Doyle
2019	J	`jnl`	QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. ACM J. Emerg. Technol. Comput. Syst. Michaela Blott, Lisa Halder, Miriam Leeser, Linda Doyle
2019	J	`jnl`	SIFO: Secure Computational Infrastructure Using FPGA Overlays. Int. J. Reconfigurable Comput. Xin Fang, Stratis Ioannidis, Miriam Leeser
2019	J	`jnl`	SIFO: Secure Computational Infrastructure using FPGA Overlays. CoRR Xin Fang, Stratis Ioannidis, Miriam Leeser
2018	Misc	`conf`	Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation. FCCM Jieming Xu, Miriam Leeser
2018	—	`conf`	Detection of Different Wireless Protocols on an FPGA with the Same Analog/RF Front End. CrownCom Suranga Handagala, Mohamed Mohamed, Jieming Xu, Marvin Onabajo, Miriam Leeser
2018	B	`conf`	Digital Pre-distortion Implemented Using FPGA. FPL Declan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley
2018	—	`conf`	Dynamic Deployment of Communication Applications to Different Hardware Platforms using Ontological Representations. HPEC Yanji Chen, Mehmet Güngör, Shweta Singh, Alex Tazin, Mieczyslaw M. Kokar, Miriam Leeser
2018	J	`jnl`	FINN- ACM Trans. Reconfigurable Technol. Syst. Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers
2018	J	`jnl`	Hardware-Software Codesign of Wireless Transceivers on Zynq Heterogeneous Systems. IEEE Trans. Emerg. Top. Comput. Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser
2018	—	`conf`	High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder. CrownCom Jieming Xu, Miriam Leeser
2018	C	`conf`	Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms. PDP Chao Liu, Miriam Leeser
2018	J	`jnl`	Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
2018	—	`conf`	Stripmap SAR Pulse Interleaved Scheduling. HPEC John Terragnoli, Miriam Leeser, Paul Monticciolo
2017	—	`conf`	A Framework for Developing Parallel Applications with high level Tasks on Heterogeneous Platforms. PMAM@PPoPP Chao Liu, Miriam Leeser
2017	—	`conf`	Accelerating big data applications using lightweight virtualization framework on enterprise cloud. HPEC Janki Bhimani, Zhengyu Yang, Miriam Leeser, Ningfang Mi
2017	B	`conf`	FIM: Performance Prediction for Parallel Computation in Iterative Data Processing Applications. CLOUD Janki Bhimani, Ningfang Mi, Miriam Leeser, Zhengyu Yang
2017	B	`conf`	FPGA modeling techniques for detecting and demodulating multiple wireless protocols. FPL Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser
2017	C	`conf`	Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser
2017	A	`conf`	Secure Function Evaluation Using an FPGA Overlay Architecture. FPGA Xin Fang, Stratis Ioannidis, Miriam Leeser
2017	—	`conf`	Using High Level GPU Tasks to Explore Memory and Communications Options on Heterogeneous Platforms. SEM4HPC@HPDC Chao Liu, Janki Bhimani, Miriam Leeser
2016	—	`conf`	Cardiac MRI compressed sensing image reconstruction with a graphics processing unit. ISMICT Majid Sabbagh, Martin Uecker, Andrew J. Powell, Miriam Leeser, Mehdi Hedjazi Moghari
2016	—	`conf`	Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus. HPEC Janki Bhimani, Miriam Leeser, Ningfang Mi
2016	J	`jnl`	High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR. IEEE Access Ramanathan Subramanian, Benjamin Drozdenko, Eric Doyle, Rameez Ahmed, Miriam Leeser, Kaushik Roy Chowdhury
2016	J	`jnl`	High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR. CoRR Ramanathan Subramanian, Benjamin Drozdenko, Eric Doyle, Rameez Ahmed, Miriam Leeser, Kaushik R. Chowdhury
2016	—	`conf`	High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC. INFOCOM Workshops Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Miriam Leeser, Kaushik R. Chowdhury
2016	B	`conf`	Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers. FPL Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser
2016	J	`jnl`	Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs. ACM Trans. Reconfigurable Technol. Syst. Xin Fang, Miriam Leeser
2016	C	`conf`	Performance prediction techniques for scalable large data processing in distributed MPI systems. IPCCC Janki Bhimani, Ningfang Mi, Miriam Leeser
2016	B	`conf`	State-Action Based Link Layer Design for IEEE 802.11b Compliant MATLAB-Based SDR. DCOSS Ramanathan Subramanian, Eric Doyle, Benjamin Drozdenko, Miriam Leeser, Kaushik R. Chowdhury
2016	—	`conf`	Unified and lightweight tasks and conduits: A high level parallel programming framework. HPEC Chao Liu, Miriam Leeser
2015	—	`conf`	Accelerating K-Means clustering with parallel implementations and GPU computing. HPEC Janki Bhimani, Miriam Leeser, Ningfang Mi
2015	—	`conf`	Balance power leakage to fight against side-channel analysis at gate level in FPGAs. ASAP Xin Fang, Pei Luo, Yunsi Fei, Miriam Leeser
2015	—	`conf`	Behavioral Non-portability in Scientific Numeric Computing. Euro-Par Yijia Gu, Thomas Wahl, Mahsa Bayati, Miriam Leeser
2015	—	`conf`	GPU implementation of reverse coordinate conversion for proteins. HPEC Mahsa Bayati, Jaydeep P. Bardhan, Miriam Leeser
2015	—	`conf`	Implementing a MATLAB-Based Self-configurable Software Defined Radio Transceiver. CrownCom Benjamin Drozdenko, Ramanathan Subramanian, Kaushik R. Chowdhury, Miriam Leeser
2015	J	`jnl`	Kernel Specialization Provides Adaptable GPU Code for Particle Image Velocimetry. IEEE Trans. Parallel Distributed Syst. Nicholas Moore, Miriam Leeser, Laurie A. Smith King
2015	—	`conf`	Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs. HPEC Xin Fang, Pei Luo, Yunsi Fei, Miriam Leeser
2015	J	`jnl`	Side-Channel Analysis of MAC-Keccak Hardware Implementations. IACR Cryptol. ePrint Arch. Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, David R. Kaeli, Miriam Leeser
2015	—	`conf`	Side-channel analysis of MAC-Keccak hardware implementations. HASP@ISCA Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, David R. Kaeli, Miriam Leeser
2014	—	`conf`	Accelerating protein coordinate conversion using GPUs. HPEC Mahsa Bayati, Jaydeep P. Bardhan, David M. King, Miriam Leeser
2014	—	`ch.`	Digital Logic. Computing Handbook, 3rd ed. (1) Miriam Leeser, James Brock
2014	A	`conf`	Make it real: Effective floating-point reasoning via exact arithmetic. DATE Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl
2014	J	`jnl`	Power Analysis Attack on Hardware Implementation of MAC-Keccak on FPGAs. IACR Cryptol. ePrint Arch. Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, Miriam Leeser, David R. Kaeli
2014	—	`conf`	Power analysis attack on hardware implementation of MAC-Keccak on FPGAs. ReConFig Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, Miriam Leeser, David R. Kaeli
2014	Misc	`conf`	Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework. FCCM Jonathon Pendlum, Miriam Leeser, Kaushik R. Chowdhury
2013	—	`conf`	FPGA-based hyperspectral covariance coprocessor for size, weight, and power constrained platforms. HPEC David A. Kusinsky, Miriam Leeser
2013	A	`conf`	Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs). IPDPS Nicholas Moore, Miriam Leeser, Laurie A. Smith King
2013	A	`conf`	Minimum energy operation for clustered island-style FPGAs. FPGA Peter Grossmann, Miriam Leeser, Marvin Onabajo
2013	—	`conf`	Vendor agnostic, high performance, double precision Floating Point division for FPGAs. HPEC Xin Fang, Miriam Leeser
2012	B	`conf`	CRUSH: Cognitive Radio Universal Software Hardware. FPL George Eichinger, Kaushik R. Chowdhury, Miriam Leeser
2012	—	`conf`	CUDA and OpenCL implementations of 3D CT reconstruction for biomedical imaging. HPEC Saoni Mukherjee, Nicholas Moore, James Brock, Miriam Leeser
2012	Misc	`conf`	Cognitive Radio Universal Software Hardware. FCCM George Eichinger, Kaushik R. Chowdhury, Miriam Leeser
2012	—	`conf`	Cognitive radio universal software hardware. DySPAN George Eichinger, Kaushik R. Chowdhury, Miriam Leeser
2012	Misc	`conf`	Implementing Murf: Accelerating Large State Space Exploration on FPGAs. FCCM Mary Ellen Tie, Miriam Leeser
2012	A	`conf`	Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation. FPGA Scott Bailie, Miriam Leeser
2012	J	`jnl`	Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA. IEEE Trans. Circuits Syst. II Express Briefs Peter Grossmann, Miriam Leeser, Marvin Onabajo
2012	J	`jnl`	VForce: An environment for portable applications on high performance systems with accelerators. J. Parallel Distributed Comput. Nicholas Moore, Miriam Leeser, Laurie A. Smith King
2011	A	`conf`	A prototype FPGA for subthreshold-optimized CMOS (abstract only). FPGA Peter Grossmann, Miriam Leeser
2011	Misc	`conf`	An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs. FCCM Jainik Kathiara, Miriam Leeser
2011	J	`jnl`	The challenges of writing portable, correct and high performance libraries for GPUs. SIGARCH Comput. Archit. News Miriam Leeser, Devon Yablonski, Dana H. Brooks, Laurie A. Smith King
2010	—	`conf`	Efficient template matching with variable size templates in CUDA. SASP Nicholas Moore, Miriam Leeser, Laurie A. Smith King
2010	—	`ed.`	Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010 GPGPU David R. Kaeli, Miriam Leeser
2010	J	`jnl`	VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. Xiaojun Wang, Miriam Leeser
2009	J	`jnl`	A truly two-dimensional systolic array FPGA implementation of QR decomposition. ACM Trans. Embed. Comput. Syst. Xiaojun Wang, Miriam Leeser
2009	—	`conf`	Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. GPGPU Perhaad Mistry, Sherman Braganza, David R. Kaeli, Miriam Leeser
2009	J	`jnl`	FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms. EURASIP J. Embed. Syst. Vinay Sriram, Miriam Leeser
2009	—	`conf`	Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. ASAP Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor
2009	J	`jnl`	Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing. EURASIP J. Embed. Syst. Ben Cordes, Miriam Leeser
2009	—	`ed.`	Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2009, Washington, DC, USA, March 8, 2009 GPGPU David R. Kaeli, Miriam Leeser
2009	—	`conf`	The Effect of Parameterization on a Reconfigurable Implementation of PIV. ERSA Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor
2008	J	`jnl`	Acknowledgment to special issue reviewers. J. Parallel Distributed Comput. David R. Kaeli, Miriam Leeser
2008	Misc	`conf`	An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. FCCM Sherman Braganza, Miriam Leeser
2008	Misc	`conf`	An FPGA Implementation of Explicit-State Model Checking. FCCM Mary Ellen Fuess, Miriam Leeser, Tim Leonard
2008	—	`conf`	An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. ASAP Sherman Braganza, Miriam Leeser
2008	J	`jnl`	Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. IEEE Trans. Very Large Scale Integr. Syst. Joshua Noseworthy, Miriam Leeser
2008	A	`conf`	Efficient FPGA implementation of qr decomposition using a systolic array architecture. FPGA Xiaojun Wang, Miriam Leeser
2008	—	`conf`	Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison. HPRCTA@SC Sherman Braganza, Miriam Leeser
2008	J	`jnl`	Special issue: General-purpose processing using graphics processing units. J. Parallel Distributed Comput. David R. Kaeli, Miriam Leeser
2007	J	`jnl`	Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems. J. Real Time Image Process. Heather Quinn, Miriam Leeser, Laurie A. Smith King
2007	Misc	`conf`	K-means Clustering for Multispectral Images Using Floating-Point Divide. FCCM Xiaojun Wang, Miriam Leeser
2007	—	`conf`	The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. ASAP Sherman Braganza, Miriam Leeser
2007	J	`jnl`	Vforce: An Extensible Framework for Reconfigurable Supercomputing. Computer Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King
2007	Misc	`conf`	Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. FCCM Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King
2006	Misc	`conf`	Advanced Components in the Variable Precision Floating-Point Library. FCCM Xiaojun Wang, Sherman Braganza, Miriam Leeser
2006	Misc	`conf`	Automatic Sliding Window Operation Optimization for FPGA-Based. FCCM Haiqian Yu, Miriam Leeser
2006	—	`conf`	Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. ERSA Joshua Noseworthy, Miriam Leeser
2006	A	`conf`	Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. FPGA Joshua Noseworthy, Miriam Leeser
2006	J	`jnl`	Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency. IEEE Trans. Multim. Peter Soderquist, Miriam Leeser, Juan Carlos Rojas
2006	J	`jnl`	Field-Programmable Gate Arrays in Embedded Systems. EURASIP J. Embed. Syst. Miriam Leeser, Scott Hauck, Russell Tessier
2006	A	`conf`	Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer. SC Ben Cordes, Miriam Leeser, Eric L. Miller, Richard W. Linderman
2006	J	`jnl`	Real-Time Particle Image Velocimetry for Feedback Loops Using FPGA Implementation. J. Aerosp. Comput. Inf. Commun. Haiqian Yu, Miriam Leeser, Gilead Tadmor, Stefan Siegel
2005	C	`conf`	Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. IEEE International Workshop on Rapid System Prototyping Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel
2005	A	`conf`	Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). FPGA Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel
2005	J	`jnl`	Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging. J. VLSI Signal Process. Miriam Leeser, Srdjan Coric, Eric L. Miller, Haiqian Yu, Marc Trepanier
2004	A	`conf`	An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. FPGA Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport
2004	—	`conf`	Dynamo: A Runtime Partitioning System. ERSA Laurie A. Smith King, Miriam Leeser, Heather Quinn
2004	Misc	`conf`	Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. FCCM Miriam Leeser, Shawn Miller, Haiqian Yu
2003	—	`conf`	Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing. Engineering of Reconfigurable Systems and Algorithms Zhihong Zhao, Miriam Leeser
2003	A*	`conf`	Programming portable optimized multimedia applications. ACM Multimedia Juan Carlos Rojas, Miriam Leeser
2003	Misc	`conf`	Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. FCCM Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis
2002	B	`conf`	A Library of Parameterized Floating-Point Modules and Their Use. FPL Pavle Belanovic, Miriam Leeser
2002	A	`conf`	Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. FPGA Srdjan Coric, Miriam Leeser, Eric L. Miller, Marc Trepanier
2001	A	`conf`	Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. FPGA Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski
2001	J	`jnl`	Design and analysis of a dynamically reconfigurable three-dimensional FPGA. IEEE Trans. Very Large Scale Integr. Syst. Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai
2001	C	`conf`	Run-Time Execution of Reconfigurable Hardware in a Java Environment. ICCD Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos
2000	J	`jnl`	A data-centric approach to high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shantanu Tarafdar, Miriam Leeser
2000	J	`jnl`	HML, a novel hardware description language and its translation to VHDL. IEEE Trans. Very Large Scale Integr. Syst. Yanbing Li, Miriam Leeser
2000	A	`conf`	Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. FPGA Ali M. Shankiti, Miriam Leeser
1998	Misc	`conf`	High Level Synthesis for Designing Custom Computing Hardware. FCCM Goran Doncev, Miriam Leeser, Shantanu Tarafdar
1998	A	`conf`	Integrating floorplanning in data-transfer based high-level synthesis. ICCAD Shantanu Tarafdar, Miriam Leeser, Zixin Yin
1998	J	`jnl`	Rothko: A Three-Dimensional FPGA. IEEE Des. Test Comput. Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky
1998	A*	`conf`	The DT-Model: High-Level Synthesis Using Data Transfers. DAC Shantanu Tarafdar, Miriam Leeser
1998	C	`conf`	Truly Rapid Prototyping Requires High-Level Synthesis. International Workshop on Rapid System Prototyping Goran Doncev, Miriam Leeser, Shantanu Tarafdar
1997	—	`conf`	Architectural Design of a Three Dimensional FPGA. ARVLSI Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai
1997	J	`jnl`	Division and square root: choosing the right implementation. IEEE Micro Peter Soderquist, Miriam Leeser
1997	C	`conf`	Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. ICCD Peter Soderquist, Miriam Leeser
1997	A*	`conf`	Optimizing the Data Cache Performance of a Software MPEG-2 Video Decoder. ACM Multimedia Peter Soderquist, Miriam Leeser
1997	B	`conf`	Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. FPL Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky
1996	J	`jnl`	Area and Performance Tradeoffs in Floating-Point Divide and Square-Root Implementations. ACM Comput. Surv. Peter Soderquist, Miriam Leeser
1995	C	`conf`	An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. IEEE Symposium on Computer Arithmetic Peter Soderquist, Miriam Leeser
1995	J	`jnl`	An Automaton Model for Scheduling Constraints in Synchronous Machines. IEEE Trans. Computers Andrés Takach, Wayne H. Wolf, Miriam Leeser
1995	C	`conf`	Verification of a subtractive radix-2 square root algorithm and implementation. ICCD Miriam Leeser, John W. O'Leary
1995	J	`jnl`	Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. IEEE Trans. Software Eng. Mark D. Aagaard, Miriam Leeser
1994	J	`jnl`	A Methodology for Efficient Hardware Verification. Formal Methods Syst. Des. Mark D. Aagaard, Miriam Leeser
1994	—	`conf`	Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. TPCD John W. O'Leary, Miriam Leeser, Jason Hickey, Mark D. Aagaard
1994	J	`jnl`	PBS: proven Boolean simplification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mark D. Aagaard, Miriam Leeser
1994	—	`conf`	Reasoning About Pipelines with Structural Hazards. TPCD Mark D. Aagaard, Miriam Leeser
1994	A	`conf`	Simulation of digital circuits in the presence of uncertainty. ICCAD Mark H. Linderman, Miriam Leeser
1993	C	`conf`	A Framework for Specifying and Designing Pipelines. ICCD Mark D. Aagaard, Miriam Leeser
1993	—	`conf`	HML: A Hardware Description Language Based on Standard ML. CHDL John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark D. Aagaard
1993	J	`jnl`	High level synthesis and generating FPGAs with the BEDROC system. J. VLSI Signal Process. Miriam Leeser, Richard Chapman, Mark D. Aagaard, Mark H. Linderman, Stephan Meier
1993	J	`jnl`	High level synthesis and generation FPGAs with the BEDROC system. J. VLSI Signal Process. Miriam Leeser
1993	—	`conf`	Toward a Super Duper Hardware Tactic. HUG Mark D. Aagaard, Miriam Leeser, Phillip J. Windley
1992	—	`conf`	A Methodology for Reusable Hardware Proofs. TPHOLs Mark D. Aagaard, Miriam Leeser
1992	A*	`conf`	Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. CAV Mark D. Aagaard, Miriam Leeser
1991	C	`conf`	A Formally Verified System for Logic Synthesis. ICCD Mark D. Aagaard, Miriam Leeser
1991	J	`jnl`	Formally verified synthesis of combinational CMOS circuits. Integr. David A. Basin, Geoffrey M. Brown, Miriam Leeser
1990	—	`ed.`	Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings Hardware Specification, Verification and Synthesis Miriam Leeser, Geoffrey Brown
1989	—	`conf`	From Programs to Transistors: Verifying Hardware Synthesis Tools. Hardware Specification, Verification and Synthesis Geoffrey M. Brown, Miriam Leeser
1989	J	`jnl`	Reasoning about the function and timing of integrated circuits with interval temporal logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Miriam Leeser
1987	—	`—`	Reasoning about the function and timing of integrated circuits with Prolog and temporal logic. Miriam Leeser
1986	J	`jnl`	Automatic determination of signal flow through MOS transistor networks. Integr. William F. Clocksin, Miriam Leeser