Minxuan Zhang - RankMe

75 papers A* 2A 1B 3C 10Journal 18Unranked 41

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Research on the construction of a mental health management platform based on multi-source data. BDICN Jinjin Cao, Minxuan Zhang, Ting Wang
2020	J	`jnl`	FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Quan Deng, Youtao Zhang, Zhenyu Zhao, Shuzheng Zhang, Minxuan Zhang, Jun Yang
2019	A*	`conf`	LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator. DAC Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang
2018	A*	`conf`	DrAcc: a DRAM based accelerator for accurate CNN inference. DAC Quan Deng, Lei Jiang, Youtao Zhang, Minxuan Zhang, Jun Yang
2017	—	`conf`	Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks. ISPA/IUCC Naiyang Guan, Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang
2017	—	`conf`	Heterogeneous acceleration for CNN training with many integrated core. ICSPCC Lei Shan, Canqun Yang, Weixia Xu, Minxuan Zhang
2017	A	`conf`	Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. ICCAD Quan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang
2016	—	`conf`	A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network. NCCET Lei Shan, Minxuan Zhang, Lin Deng, Guohui Gong
2016	—	`conf`	A New DVFS Algorithm Design for Multi-core Processor Chip. NCCET Chengyi Zhang, Jiming Wang, Minxuan Zhang, Xiangdi Wu
2016	—	`conf`	A Novel Hybrid Last Level Cache Based on Multi-retention STT-RAM Cells. ACA Hongguang Zhang, Minxuan Zhang, Zhenyu Zhao, Shuo Tian
2016	—	`conf`	A Novel L1 Cache Based on Volatile STT-RAM. NCCET Hongguang Zhang, Minxuan Zhang
2016	—	`conf`	Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture. NCCET Lei Shan, He Wang, Weixia Xu, Canqun Yang, Minxuan Zhang
2016	—	`conf`	Hardware design of ML algorithm in MIMO-OFDM system. ICSAI Suncheng Xiang, Minxuan Zhang, Zuocheng Xing, Cang Liu
2016	—	`conf`	Sub-threshold Performance Driven Choice in Tunneling CNFETs. NCCET Hailiang Zhou, Xiantuo Tang, Minxuan Zhang, Yue Hao
2016	J	`jnl`	Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system. IEICE Electron. Express Wei Guo, Minxuan Zhang, Chaoyun Yao, Peng Li, Chaochao Feng, Hongwei Zhou
2015	J	`jnl`	Exploring partitioning methods for multicast in 3D bufferless Network on Chip. IEICE Electron. Express Chaoyun Yao, Chaochao Feng, Minxuan Zhang, Wei Guo, Shouzhong Zhu, Shaojun Wei
2015	J	`jnl`	Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system. IEICE Electron. Express Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao
2015	—	`conf`	Impact of Heavy Ion Species and Energy on SEE Characteristics of Three-Dimensional Integrated Circuit. NCCET Peng Li, Wei Guo, Zhenyu Zhao, Minxuan Zhang
2015	—	`conf`	Improved access pattern for ROB soft error rate mitigation based on 3D integration technology. 3DIC Chao Song, Minxuan Zhang
2015	—	`conf`	Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture. NCCET Chao Song, Minxuan Zhang
2015	—	`conf`	Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC. NCCET Quan Deng, Minxuan Zhang, Zhenyu Zhao, Peng Li
2015	—	`conf`	Partitioning Methods for Multicast in Bufferless 3D Network on Chip. NCCET Chaoyun Yao, Chaochao Feng, Minxuan Zhang, Wei Guo, Shouzhong Zhu, Shaojun Wei
2015	J	`jnl`	SEU hardened layout design for SRAM cells based on SEU reversal. IEICE Electron. Express Peng Li, Wei Guo, Zhenyu Zhao, Minxuan Zhang, Quan Deng
2015	—	`conf`	Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling. NCCET Wei Guo, Minxuan Zhang, Peng Li, Chaoyun Yao, Hongwei Zhou
2015	J	`jnl`	Towards high-performance packet processing on commodity multi-cores: current issues and future directions. Sci. China Inf. Sci. Lu Tang, Jinli Yan, Zhigang Sun, Tao Li, Minxuan Zhang
2014	C	`conf`	Assimilating Cleaning Operations with Flash-Level Parallelism for NAND Flash-Based Devices. CIT Ronghui Wang, Zhiguang Chen, Nong Xiao, Minxuan Zhang, Weihua Dong
2014	J	`jnl`	Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells. IEICE Electron. Express Peng Li, Minxuan Zhang, Weicheng Zhang, Zhenyu Zhao, Chao Song, Hua Fan
2014	J	`jnl`	Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. IEEE Trans. Very Large Scale Integr. Syst. Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei
2013	J	`jnl`	Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. IEEE Trans. Very Large Scale Integr. Syst. Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Zuocheng Xing
2013	—	`conf`	An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors. ASICON Anwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang
2013	J	`jnl`	Architecture and Implementation of a Reduced EPIC Processor. IEICE Trans. Inf. Syst. Jun Gao, Minxuan Zhang, Zuocheng Xing, Chaochao Feng
2013	—	`conf`	Wormhole Bubble in Torus Networks. NCCET Yongqing Wang, Minxuan Zhang
2012	J	`jnl`	A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip. IEICE Trans. Inf. Syst. Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang
2012	J	`jnl`	A single-cycle output buffered router with layered switching for Networks-on-Chips. Comput. Electr. Eng. Yancang Chen, Zhonghai Lu, Lunguo Xie, Jinwen Li, Minxuan Zhang
2012	J	`jnl`	Accurate and Simplified Prediction of L2 Cache Vulnerability for Cost-Efficient Soft Error Protection. IEICE Trans. Inf. Syst. Yu Cheng, Anguo Ma, Minxuan Zhang
2012	—	`conf`	Adaptive Bubble Scheme with Minimal Buffers in Torus Networks. HPCC-ICESS Yongqing Wang, Minxuan Zhang, Qingchao Yu, Zhengbin Pang
2012	J	`jnl`	Adaptive Capacity Sharing through Probabilistic Controlled Placement. J. Comput. Xianju Yang, Peixiang Yan, Jiang Jiang, Minxuan Zhang
2012	C	`conf`	An Efficient Hardware Random Number Generator Based on the MT Method. CIT Yuan Li, Jiang Jiang, Hanqiang Cheng, Minxuan Zhang, Shaojun Wei
2012	—	`conf`	PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture. NAS Anwen Huang, Jun Gao, Wei Guo, Wenqiang Shi, Minxuan Zhang, Jiang Jiang
2012	—	`conf`	Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. FPT Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang, Shaojun Wei
2012	J	`jnl`	Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip. IEICE Trans. Inf. Syst. Chaochao Feng, Zhonghai Lu, Axel Jantsch, Minxuan Zhang, Xianju Yang
2011	—	`conf`	A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. ISVLSI Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch
2011	C	`conf`	Accelerating the Extraction of Representative Behaviors of Programs with Dynamic Binary Translation. HPCC Tianlei Zhao, Jiang Jiang, Guitao Fu, Shubo Qi, Xiaomin Jia, Minxuan Zhang
2011	J	`jnl`	BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs. Comput. Informatics Xiaomin Jia, Jiang Jiang, Yongwen Wang, Shubo Qi, Tianlei Zhao, Guitao Fu, Minxuan Zhang
2011	—	`conf`	Characterizing Time-Varying Behavior and Predictability of Cache AVF. INCoS Yu Cheng, Yongwen Wang, Zuocheng Xing, Minxuan Zhang
2011	—	`conf`	Evaluation of deflection routing on various NoC topologies. ASICON Chaochao Feng, Jinwen Li, Zhonghai Lu, Axel Jantsch, Minxuan Zhang
2011	B	`conf`	Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. FPL Yuan Li, Paul Chow, Jiang Jiang, Minxuan Zhang
2011	B	`conf`	Timing-Driven Routing of High Fanout Nets. FPL Xun Chen, Jianwen Zhu, Minxuan Zhang
2010	—	`conf`	A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. ISVLSI Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang
2010	C	`conf`	A high performance router with dynamic buffer allocation for on-chip interconnect networks. ICCD Shubo Qi, Minxuan Zhang, Jinwen Li, Tianlei Zhao, Chengyi Zhang, Shaoqing Li
2010	—	`conf`	A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip. NoCArc@MICRO Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang
2010	J	`jnl`	Dynamic Program Behavior Identification for High Performance CMPs with Private LLCs. IEICE Trans. Inf. Syst. Xiaomin Jia, Pingjing Lu, Caixia Sun, Minxuan Zhang
2010	—	`conf`	FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip. SoCC Chaochao Feng, Zhonghai Lu, Axel Jantsch, Jinwen Li, Minxuan Zhang
2010	—	`conf`	Low Power Design for a Multi-core Multi-thread Microprocessor. GreenCom/CPSCom Yongwen Wang, Qianbing Zheng, Qiang Dou, Minxuan Zhang
2010	J	`jnl`	Opitimization of tunneling carbon nanotube-FETs based on stair-case doping strategy. Sci. China Inf. Sci. Hailiang Zhou, Jiang Jiang, Minxuan Zhang, Liang Fang
2010	—	`conf`	Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material. ISVLSI Zhou Hailiang, Minxuan Zhang, Fang Liang, Hao Yue
2010	C	`conf`	Phase Characterization and Classification for Micro-architecture Soft Error. EUC Yu Cheng, Anguo Ma, Yuxing Tang, Minxuan Zhang
2010	C	`conf`	Towards Online Application Cache Behaviors Identification in CMPs. HPCC Xiaomin Jia, Jiang Jiang, Tianlei Zhao, Shubo Qi, Minxuan Zhang
2009	—	`conf`	A Global Replacement Based on Actual Set Association. ICESS Peixiang Yan, Xianju Yang, Minxuan Zhang
2008	—	`conf`	Dimensional Bubble Flow Control and Fully Adaptive Routing in the 2-D Mesh Network on Chip. EUC (1) Canwen Xiao, Minxuan Zhang, Yong Dou, Zhitong Zhao
2007	C	`conf`	A Parallel Infrastructure on Dynamic EPIC SMT and Its Speculation Optimization. ISPA Qingying Deng, Minxuan Zhang, Jiang Jiang
2007	C	`conf`	A Parallel Infrastructure on Dynamic EPIC SMT. ICA3PP Qingying Deng, Minxuan Zhang, Jiang Jiang
2007	—	`conf`	A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching. ICESS Xinhua Tian, Minxuan Zhang
2007	—	`conf`	A Unified Compressed Cache Hierarchy With Partial Cache Line Prefetching Used for SMT Processor. CDES Tian Xinhua, Minxuan Zhang
2007	B	`conf`	Hardware-Based Multicast with Global Load Balance on k-ary n-trees. ICPP Quanbao Sun, Minxuan Zhang, Liquan Xiao
2007	—	`conf`	Look-Ahead Adaptive Routing on APPT Quanbao Sun, Liquan Xiao, Minxuan Zhang
2007	—	`conf`	Register File Management and Compiler Optimization on EDSMT. ISPA Workshops Qingying Deng, Minxuan Zhang, Jiang Jiang
2006	—	`conf`	An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. Asia-Pacific Computer Systems Architecture Conference Chengyi Zhang, Hongwei Zhou, Minxuan Zhang, Zuocheng Xing
2006	C	`conf`	Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy. PDCAT Caixia Sun, Hong-Wei Tang, Minxuan Zhang
2006	—	`conf`	Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors. Asia-Pacific Computer Systems Architecture Conference Caixia Sun, Hong-Wei Tang, Minxuan Zhang
2005	—	`conf`	A Fetch Policy Maximizing Throughput and Fairness for Two-Context SMT Processors. APPT Caixia Sun, Hong-Wei Tang, Minxuan Zhang
2005	—	`conf`	Detecting Memory Access Errors with Flow-Sensitive Conditional Range Analysis. ICESS Yimin Xia, Jun Luo, Minxuan Zhang
2005	C	`conf`	Enhancing DCache Warn Fetch Policy for SMT Processors. ISPA Minxuan Zhang, Caixia Sun
2004	—	`conf`	Dual-Stack Return Address Predictor. ICESS Caixia Sun, Minxuan Zhang
2003	—	`conf`	Reconfigurable Cipher Processing Framework and Implementation. APPT Jingfei Jiang, Xiaoqiang Ni, Minxuan Zhang