Minoru Watanabe

153 papers A 7B 7C 31Misc 4Journal 6Unranked 97

Year	Rank	Type	Title / Venue / Authors
2026	C	`conf`	An implementation of a quantum algorithm on a Cyclone FPGA. ICCE Haruto Kurokawa, Minoru Watanabe, Nobuya Watanabe
2026	C	`conf`	Flip-flop resource expansion method for FPGAs using latches created on look-up tables. ICCE Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe
2026	C	`conf`	Mono Instruction Set Computer design using a high-level hardware description language. ICCE Nobuya Watanabe, Minoru Watanabe
2026	C	`conf`	OpenOCD-Compliant Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Array VLSIs. ICCE Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe
2026	J	`jnl`	Programmable Clock Distribution Using Switching Matrices for Field Programmable Gate Arrays. IEEE Access Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe
2026	C	`conf`	Soft-error measurement for a radiation-hardened RISC-V processor. ICCE Masato Isobe, Minoru Watanabe, Nobuya Watanabe
2025	—	`conf`	Delay adjustment circuit for a triple modular redundant communication system used for radiation-hardened robots. CIIS Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA. ICCE Ayumu Ogura, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Development of a Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Arrays. ICCE Naoki Nagamine, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Fast-Neutron Soft-Error Tolerance of a Radiation-Hardened Repairable Field Programmable Gate Array. ICCE Minoru Watanabe, Makoto Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shingo Tamaki, Isao Murata, Sachie Kusaka
2025	C	`conf`	Implementation of Mono Instruction Set Computer with Small Register Files. ICCE Soma Imai, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI. ICCE Seiji Ohashi, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Radiation-Hardened Triple Modular Redundant Serial Communication System Using Triple Communication Lines. ICCE Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Realization of Wafer-Scale VLSI Using Optical Configuration Architecture. ICCE Atsushi Takata, Minoru Watanabe, Nobuya Watanabe
2025	C	`conf`	Triple Modular Redundancy Logic Design from High-Level Hardware Description. ICCE Nobuya Watanabe, Minoru Watanabe
2024	—	`conf`	Analysis of Clock Tree Buffer Degradation Caused by Radiation. ARC Minoru Watanabe
2024	C	`conf`	Application design system for high-speed dynamically reconfigurable gate arrays. ICCE Nobuya Watanabe, Ryoya Ishitani, Minoru Watanabe
2024	C	`conf`	Fast-neutron soft-error tolerance experimentation with a radiation-hardened optically reconfigurable gate array. ICCE Minoru Watanabe, Makoto Inami Kobayashi, Mitsutaka Isobe, Kunihiro Ogawa, Shigeo Matsuyama, Misako Miwa
2024	C	`conf`	Holographic memory formed by different laser wavelengths in laser combiner system for optically reconfigurable gate array. ICCE Akifumi Ogiwara, Minoru Watanabe
2024	C	`conf`	Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory. ICCE Sae Goto, Minoru Watanabe, Akifumi Ogiwara, Nobuya Watanabe
2024	C	`conf`	Remote monitoring system for optically reconfigurable gate arrays in radiation environments. ICCE Utsuki Sekioka, Minoru Watanabe, Nobuya Watanabe
2024	—	`conf`	Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI. SOCC Shintaro Takatsuki, Minoru Watanabe, Nobuya Watanabe
2024	—	`conf`	Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI. ASAP Yuki Shimamura, Minoru Watanabe, Nobuya Watanabe
2024	C	`conf`	Wafer-scale VLSI realization using programmable architecture. ICCE Atsushi Takata, Minoru Watanabe, Nobuya Watanabe
2023	—	`conf`	An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit. SOCC Masashi Tsujino, Minoru Watanabe, Nobuya Watanabe
2023	—	`conf`	Multi-context-scrubbing operation for a 1-bit counter circuit. NEWCAS Kakeru Ando, Minoru Watanabe, Nobuya Watanabe
2023	—	`conf`	Radiation-hardened stabilized power supply unit based on bipolar transistors. ICM Takato Tanizawa, Minoru Watanabe
2023	C	`conf`	Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock. ISCAS Minoru Watanabe
2023	C	`conf`	Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor. ICCE Daisuke Bamba, Minoru Watanabe, Nobuya Watanabe
2022	—	`conf`	Convolutional neural network implementations using Vitis AI. CCWC Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya
2022	—	`conf`	Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration. APCCAS Sae Goto, Minoru Watanabe, Nobuya Watanabe
2022	—	`conf`	Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI. ICECS 2022 Kaho Yamada, Takeshi Okazaki, Minoru Watanabe, Nobuya Watanabe
2021	C	`conf`	Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs. ISCAS Kurea Murakami, Minoru Watanabe
2021	—	`conf`	Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation. FPT Hirotoshi Ito, Minoru Watanabe
2019	C	`conf`	FPGA implementation of a robot control algorithm. ETFA Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano
2019	—	`conf`	Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation. APCCAS Masaki Watanabe, Minoru Watanabe
2019	—	`conf`	Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array. SoCC Hirotoshi Ito, Minoru Watanabe
2018	—	`conf`	A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory. AHS Takumi Fujimori, Minoru Watanabe
2018	—	`ch.`	Advanced Devices and Architectures. Principles and Structures of FPGAs Masato Motomura, Masanori Hariyama, Minoru Watanabe
2018	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Minoru Watanabe
2018	C	`conf`	High total-ionizing-dose tolerance field programmable gate array. ISCAS Takumi Fujimori, Minoru Watanabe
2017	—	`conf`	500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA. AHS Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara
2017	—	`conf`	Holographic Memory Calculation FPGA Accelerator for Optically Reconfigurable Gate Arrays. DASC/PiCom/DataCom/CyberSciTech Takumi Fujimori, Minoru Watanabe
2017	—	`conf`	Multi-context scrubbing method. MWSCAS Takumi Fujimori, Minoru Watanabe
2017	—	`conf`	Optically reconfigurable gate array platform for mono-instruction set computer architecture. CCWC Hiroki Shinba, Minoru Watanabe
2017	—	`conf`	Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array. SoCC Takumi Fujimori, Minoru Watanabe
2016	—	`conf`	A 200 Mrad Radiation Tolerance of a Polymer-Dispersed Liquid Crystal Holographic Memory. HPCC/SmartCity/DSS Yoshizumi Ito, Minoru Watanabe, Akifumi Ogiwara
2016	—	`conf`	Direct optical communication on an optically reconfigurable gate array. FGCT Shinya Furukawa, Ili Shairah Abdul Halim, Minoru Watanabe, Fuminori Kobayashi
2016	C	`conf`	Full FPGA game machine. ICCE Takumi Fujimori, Minoru Watanabe
2016	—	`conf`	Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays. ICCSE Bharat Ramanathan, Minoru Watanabe
2016	Misc	`conf`	Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays. VLSID Tomoya Akabe, Minoru Watanabe
2015	—	`conf`	FPGA Trax Solver based on a neural network design. FPT Takumi Fujimori, Tomoya Akabe, Yoshizumi Ito, Kouta Akagi, Shinya Furukawa, Hiroki Shinba, Aoi Tanibata, Minoru Watanabe
2015	—	`conf`	Holographic scrubbing technique for a programmable gate array. AHS Minoru Watanabe, Takumi Fujimori
2015	—	`conf`	Parallel-Operation-Oriented Optically Reconfigurable Gate Array. ARCS Takumi Fujimori, Minoru Watanabe
2015	—	`conf`	Sustainable advantage of a parallel configuration in an optical FPGA. SII Minoru Watanabe
2015	—	`conf`	Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array. ARC Retsu Moriwaki, Hiroyuki Ito, Kouta Akagi, Minoru Watanabe, Akifumi Ogiwara
2014	—	`conf`	Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation. ARC Takashi Yoza, Minoru Watanabe
2014	C	`conf`	Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture. ISCAS Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito
2014	—	`conf`	Optically reconfigurable gate array with an angle-multiplexed holographic memory. ACM Great Lakes Symposium on VLSI Retsu Moriwaki, Hikaru Maekawa, Akifumi Ogiwara, Minoru Watanabe
2014	—	`conf`	Radiation Tolerance of Color Configuration on an Optically Reconfigurable Gate Array. IPDPS Workshops Takumi Fujimori, Minoru Watanabe
2013	C	`conf`	0.18 μm CMOS process photodiode memory. ISCAS Takayuki Kubota, Minoru Watanabe
2013	—	`conf`	Color configuration method for an optically reconfigurable gate array. FPT Takumi Fujimori, Minoru Watanabe
2013	—	`conf`	Dependability-Increasing Method of Processors under a Space Radiation Environment. ARC Yuya Shirahashi, Minoru Watanabe
2013	C	`conf`	Dependability-increasing technique for a multi-context optically reconfigurable gate array. ISCAS Akira Tanigawa, Minoru Watanabe
2013	—	`conf`	FPGA Blokus Duo Solver using a massively parallel architecture. FPT Takashi Yoza, Retsu Moriwaki, Yuki Torigai, Yuki Kamikubo, Takayuki Kubota, Takahiro Watanabe, Takumi Fujimori, Hiroyuki Ito, Masato Seo, Kouta Akagi, Yuichiro Yamaji, Minoru Watanabe
2013	—	`conf`	Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method. AHS Yuichiro Yamaji, Minoru Watanabe
2013	—	`conf`	Fourier transformation on an optically reconfigurable gate array. MWSCAS Hiroyuki Ito, Minoru Watanabe
2013	B	`conf`	Image recognition operation on a dynamically reconfigurable vison architecture. FPL Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito
2012	J	`jnl`	0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. SIGARCH Comput. Archit. News Takahiro Watanabe, Minoru Watanabe
2012	—	`conf`	0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. ISVLSI Takahiro Watanabe, Minoru Watanabe
2012	—	`conf`	A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. AHS Takashi Yoza, Minoru Watanabe
2012	B	`conf`	A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. FPL Takashi Yoza, Minoru Watanabe
2012	—	`conf`	A Uniform Partitioning Method for Mono-Instruction Set Computer (MISC). NBiS Hiroyuki Ito, Minoru Watanabe
2012	—	`conf`	Gray-level image recognition on a dynamically reconfigurable vision architecture. SoCC Yuki Kamikubo, Minoru Watanabe, Shoji Kawahito
2012	—	`conf`	High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. IPDPS Workshops Takahiro Watanabe, Minoru Watanabe
2012	—	`conf`	Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. MWSCAS Takahiro Watanabe, Minoru Watanabe
2012	—	`conf`	Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. ARC Takahiro Watanabe, Minoru Watanabe
2011	—	`conf`	A 144-configuration context MEMS optically reconfigurable gate array. SoCC Yuichiro Yamaji, Minoru Watanabe
2011	J	`jnl`	A MEMS writer system embedded for a programmable optically reconfigurable gate array. SIGARCH Comput. Archit. News Shinya Kubota, Minoru Watanabe
2011	—	`conf`	An FPGA Connect6 Solver with a two-stage pipelined evaluation. FPT Takahiro Watanabe, Retsu Moriwaki, Yuichiro Yamaji, Yuki Kamikubo, Yuki Torigai, Yuki Nihira, Takashi Yoza, Yumiko Ueno, Yuji Aoyama, Minoru Watanabe
2011	B	`conf`	Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. FPL Takahiro Watanabe, Minoru Watanabe
2011	J	`jnl`	Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control. ACM Trans. Reconfigurable Technol. Syst. Mao Nakajima, Minoru Watanabe
2011	—	`conf`	MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays. ARC Hironobu Morita, Minoru Watanabe
2011	—	`conf`	Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory. AHS Takayuki Mabuchi, Minoru Watanabe, Akifumi Ogiwara, Fuminori Kobayashi
2011	—	`conf`	Triple module redundancy scheme on an optically reconfigure gate array. ISOCC Yuki Torigai, Minoru Watanabe
2010	C	`conf`	A 100-context optically reconfigurable gate array. ISCAS Mao Nakajima, Minoru Watanabe
2010	—	`conf`	A 64-context MEMS optically reconfigurable gate array. FPT Yuichiro Yamaji, Minoru Watanabe
2010	—	`conf`	Acceleration method of optical reconfigurations using analog configuration contexts. AHS Yuji Aoyama, Minoru Watanabe
2010	—	`conf`	Binary MEMS Optically Reconfigurable Gate Array. ACIS-ICIS Hironobu Morita, Minoru Watanabe
2010	B	`conf`	Dynamically Reconfigurable Vision-Chip Architecture. FPL Maki Yasuda, Minoru Watanabe
2010	—	`conf`	Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array. SoCC Yuji Aoyama, Minoru Watanabe
2010	—	`conf`	MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment. ARC Daisaku Seto, Minoru Watanabe
2010	—	`conf`	Othello Solver based on a soft-core MIMD processor array. FPT Takayuki Mabuchi, Takahiro Watanabe, Retsu Moriwaki, Yuji Aoyama, Amarjargal Gundjalam, Yuichiro Yamaji, Hironari Nakada, Minoru Watanabe
2010	—	`conf`	Partial Block-by-Block Reconfiguration for a Dynamic Optically Reconfigurable Gate Array. ERSA Daisaku Seto, Minoru Watanabe
2010	—	`conf`	Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays. DFT Daisaku Seto, Minoru Watanabe
2010	—	`conf`	Recovery method for a turn-off failure mode of a laser array on an ORGA. AHS Daisaku Seto, Minoru Watanabe
2009	—	`conf`	A 13.75 ns Holographic Reconfiguration of an Optically Differential Reconfigurable Gate Array. IIH-MSP Mao Nakajima, Minoru Watanabe
2009	—	`conf`	A 16-context Optically Reconfigurable Gate Array. ASAP Mao Nakajima, Minoru Watanabe
2009	—	`conf`	A Multi-Context Programmable Optically Reconfigurable Gate Array. ERSA Shinya Kubota, Minoru Watanabe
2009	—	`conf`	A Sixteen-Context Dynamic Optically Reconfigurable Gate Array. AHS Mao Nakajima, Minoru Watanabe
2009	—	`conf`	A nine-context programmable optically reconfigurable gate array with semiconductor lasers. ACM Great Lakes Symposium on VLSI Shinya Kubota, Minoru Watanabe
2009	—	`conf`	Alignment compensation method for an optically reconfigurable gate array. ERSA Hironobu Morita, Minoru Watanabe
2009	—	`conf`	An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. ASP-DAC Daisaku Seto, Minoru Watanabe
2009	—	`conf`	Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory. AHS Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara
2009	—	`conf`	Fast Optical Reconfiguration of a Nine-Context DORGA. ARC Mao Nakajima, Minoru Watanabe
2009	C	`conf`	Fast Reconfiguration Experiments of an Optically Differential Reconfigurable Gate Array with Nine Configuration Contexts. ISCAS Mao Nakajima, Minoru Watanabe
2009	—	`conf`	Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. SAMOS Shinichi Kato, Minoru Watanabe
2009	B	`conf`	Mems optically reconfigurable gate array. FPL Hironobu Morita, Minoru Watanabe
2009	—	`conf`	Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory. ERSA Takayuki Mabuchi, Kenji Miyashiro, Minoru Watanabe, Akifumi Ogiwara
2008	—	`conf`	A 770ns Holographic Reconfiguration of a Four-Context DORGA. ERSA Mao Nakajima, Minoru Watanabe
2008	A	`conf`	A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. IPDPS Mao Nakajima, Daisaku Seto, Minoru Watanabe
2008	—	`conf`	A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations. AHS Kouhi Shinohara, Minoru Watanabe
2008	—	`conf`	A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. ISVLSI Daisaku Seto, Minoru Watanabe
2008	—	`conf`	An 11, 424-gate dynamic optically reconfigurable gate array VLSI. FPT Mao Nakajima, Minoru Watanabe
2008	Misc	`conf`	An Acceleration and Optimization Method for Optical Reconfiguration. VLSI Design Minoru Watanabe, Naoki Yamaguchi
2008	Misc	`conf`	An Optical Reconfiguration System with Four Contexts. VLSI Design Naoki Yamaguchi, Minoru Watanabe
2008	—	`conf`	An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays. FPT Takayuki Mabuchi, Minoru Watanabe
2008	—	`conf`	Analysis of retention time under multi-configuration on a DORGA. SoCC Daisaku Seto, Minoru Watanabe
2008	A	`conf`	Defect tolerance of holographic configurations in ORGAs. IPDPS Kouhi Shinohara, Minoru Watanabe
2008	—	`conf`	Dynamic holographic reconfiguration on a four-context ODRGA. ASAP Mao Nakajima, Minoru Watanabe
2008	—	`conf`	Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI. FPT Shinichi Kato, Minoru Watanabe
2008	—	`conf`	MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. ERSA Fuminori Kobayashi, Yasuyuki Morikawa, Minoru Watanabe
2007	—	`conf`	272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. ERSA Minoru Watanabe, Takenori Shiki, Fuminori Kobayashi
2007	—	`conf`	A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ASP-DAC Minoru Watanabe, Fuminori Kobayashi
2007	—	`conf`	A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array. FPT Mao Nakajima, Minoru Watanabe
2007	A	`conf`	A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. IPDPS Rio Miyazaki, Minoru Watanabe, Fuminori Kobayashi
2007	—	`conf`	An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. SoCC Minoru Watanabe
2007	C	`conf`	Holographic memory reconfigurable VLSI. ISCAS Minoru Watanabe, Fuminori Kobayashi
2007	—	`conf`	Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. ERSA Minoru Watanabe
2007	—	`conf`	Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture. FPT Daisaku Seto, Minoru Watanabe
2006	—	`conf`	A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. ARC Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. ASP-DAC Minoru Watanabe, Fuminori Kobayashi
2006	B	`conf`	A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. FPL Minoru Watanabe, Fuminori Kobayashi
2006	A	`conf`	An optically differential reconfigurable gate array with a holographic memory. IPDPS Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
2006	—	`conf`	Differential Reconfiguration Architecture suitable for a Holographic Memory. ERSA Minoru Watanabe, Mototsugu Miyano, Fuminori Kobayashi
2006	—	`conf`	Logic Synthesis and Place-and-Route Environment for ORGAs. ERSA Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	Optically Reconfigurable Gate Arrays vs. ASICs. APCCAS Minoru Watanabe, Fuminori Kobayashi
2006	A	`conf`	Power consumption advantage of a dynamic optically reconfigurable gate array. IPDPS Minoru Watanabe, Fuminori Kobayashi
2006	—	`conf`	Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. ERSA Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. ISCAS (2) Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. FPT Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	An Improved Dynamic Optically Reconfigurable Gate Array. ISVLSI Minoru Watanabe, Fuminori Kobayashi
2005	A	`conf`	An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. IPDPS Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. ISVLSI Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
2005	—	`conf`	Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. FPT Mototsugu Miyano, Minoru Watanabe, Fuminori Kobayashi
2004	B	`conf`	A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. FPL Minoru Watanabe, Fuminori Kobayashi
2004	Misc	`conf`	An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. VLSI Design Minoru Watanabe, Fuminori Kobayashi
2004	—	`conf`	An optically differential reconfigurable gate array using a 0.18 μm CMOS process. SoCC Minoru Watanabe, Fuminori Kobayashi
2004	—	`conf`	Testing Method for Optical Connections Using Gate Array Structure in ORGAs. ERSA Minoru Watanabe, Fuminori Kobayashi
2004	—	`conf`	Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. ERSA Minoru Watanabe, Fuminori Kobayashi
2003	J	`jnl`	An FPGA Implementation of Finite Physical Quantity Neural Network. J. Robotics Mechatronics Takashi Sotohebo, Minoru Watanabe, Funtinori Kobayashi
2003	A	`conf`	An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. IPDPS Minoru Watanabe, Fuminori Kobayashi
2002	—	`conf`	An optically differential reconfigurable gate array and its power consumption estimation. FPT Minoru Watanabe, Fuminori Kobayashi