Minoru Saeki

16 papers A 4Journal 11Unranked 1
YearRankTypeTitle / Venue / Authors
2016 J jnl
Asymmetric Leakage from Multiplier and Collision-Based Single-Shot Side-Channel Attack.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki
2015 — conf
Two Operands of Multipliers in Side-Channel Attack.
COSADE
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki
2015 J jnl
Two Operands of Multipliers in Side-Channel Attack.
IACR Cryptol. ePrint Arch.
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki
2014 J jnl
On measurable side-channel leaks inside ASIC design primitives.
J. Cryptogr. Eng.
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2013 A conf
On Measurable Side-Channel Leaks Inside ASIC Design Primitives.
CHES
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2013 J jnl
On Measurable Side-Channel Leaks inside ASIC Design Primitives.
IACR Cryptol. ePrint Arch.
Takeshi Sugawara, Daisuke Suzuki, Minoru Saeki, Mitsuru Shiozaki, Takeshi Fujino
2011 J jnl
How to Decide Selection Functions for Power Analysis: From the Viewpoint of Hardware Architecture of Block Ciphers.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Tsutomu Matsumoto
2010 J jnl
A Design Methodology for a DPA-Resistant Circuit with RSL Techniques.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto
2009 A conf
A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques.
CHES
Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
2008 J jnl
An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Suzuki, Minoru Saeki
2008 J jnl
Security Evaluations of MRSL and DRSL Considering Signal Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Minoru Saeki, Daisuke Suzuki
2007 J jnl
Leakage Analysis of DPA Countermeasures at the Logic Level.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Minoru Saeki, Daisuke Suzuki, Tetsuya Ichikawa
2007 J jnl
Random Switching Logic: A New Countermeasure against DPA and Second-Order DPA at the Logic Level.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
2006 A conf
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style.
CHES
Daisuke Suzuki, Minoru Saeki
2005 A conf
DPA Leakage Models for CMOS Logic Circuits.
CHES
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa
2004 J jnl
Random Switching Logic: A Countermeasure against DPA based on Transition Probability.
IACR Cryptol. ePrint Arch.
Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa