Mingyu Wang

19 papers A* 5B 2C 1Journal 6Unranked 5
YearRankTypeTitle / Venue / Authors
2026 A* conf
LRM-GPU: Alleviating Synchronization Overhead for Multi-Chiplet GPU Architecture.
HPCA
Baiqing Zhong, Zhirong Ye, Xiaojie Li, Peilin Wang, Haiqiu Huang, Zhaolin Li, Zhiyi Yu, Mingyu Wang
2026 — conf
NBCache: An Efficient and Scalable Non-Blocking Cache for Coherent Multi-Chiplet Systems.
ASP-DAC
Zhirong Ye, Yongchang Zhang, Peilin Wang, Tao Lu, Zhaolin Li, Zhiyi Yu, Mingyu Wang
2026 J jnl
UniCNet: Unified Cycle-Accurate Simulation for Composable Chiplet Network With Modular Design-Integration Workflow.
IEEE Comput. Archit. Lett.
Peilin Wang, Mingyu Wang, Zhirong Ye, Tao Lu, Zhiyi Yu
2025 J jnl
A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms.
IEEE Trans. Circuits Syst. II Express Briefs
Haiqiu Huang, Mingyu Wang, Xiaojie Li, Baiqing Zhong, Zeqi Yang, Tao Lu, Yicong Zhang, Zhiyi Yu
2025 A* conf
C3ache: Towards Hierarchical Cache-Centric Computing for Sparse Matrix Multiplication on GPGPUs.
MICRO
Xiaojie Li, Mingyu Wang, Baiqing Zhong, Haiqiu Huang, Guangjie Cao, Zhiyi Yu
2025 J jnl
CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yao Qin, Mingyu Wang, Jiahua Yan, Tao Lu, Zhiyi Yu
2025 A* conf
MagiCache: A Virtual In-Cache Computing Engine.
ISCA
Renhao Fan, Yikai Cui, Weike Li, Mingyu Wang, Zhaolin Li
2024 A* conf
Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations.
MICRO
Yicong Zhang, Mingyu Wang, Wangguang Wang, Yangzhan Mai, Haiqiu Huang, Zhiyi Yu
2024 — conf
BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM.
ISVLSI
Xiaojie Li, Mingyu Wang, Yangzhan Mai, Yicong Zhang, Baiqing Zhong, Zhiyi Yu
2024 — conf
DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s.
ISVLSI
Yukun Wei, Mingyu Wang, Haiqiu Huang, Wangguang Wang, Zhiyi Yu
2023 C conf
A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips.
ISCAS
Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu
2023 — conf
A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference.
ISVLSI
Baiqing Zhong, Mingyu Wang, Chuanghao Zhang, Yangzhan Mai, Xiaojie Li, Zhiyi Yu
2023 J jnl
A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs
Chuanghao Zhang, Mingyu Wang, Yangzhan Mai, Chengcheng Tang, Zhiyi Yu
2023 B conf
A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems.
ICPADS
Xiaoran Zhang, Mingyu Wang, Yicong Zhang, Tao Lu, Zhiyi Yu
2023 B conf
LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs.
ICPADS
Wangguang Wang, Mingyu Wang, Yicong Zhang, Yukun Wei, Zhiyi Yu
2023 A* conf
MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference.
MICRO
Renhao Fan, Yikai Cui, Qilin Chen, Mingyu Wang, Youhui Zhang, Weimin Zheng, Zhaolin Li
2023 J jnl
TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs.
IEEE Trans. Very Large Scale Integr. Syst.
Yicong Zhang, Mingyu Wang, Yangzhan Mai, Zhiyi Yu
2022 — conf
3D-NWA: A Nested-Winograd Accelerator for 3D CNNs.
ICTA
Huafeng Ye, Huipeng Deng, Jian Wang, Mingyu Wang, Zhiyi Yu
2017 J jnl
A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures.
IEEE Trans. Very Large Scale Integr. Syst.
Mingyu Wang, Zhaolin Li