Mingyang Kou

11 papers A* 5C 1Journal 3Unranked 2
YearRankTypeTitle / Venue / Authors
2025 A* conf
GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAs.
DAC
Mingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao
2025 A* conf
Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography.
DAC
Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Nengyong Zhu, Hailong Yao
2025 C conf
NaviMap: Partial Order-Guided Neural Architecture via Deep Q-Networks for Efficient CGRA Mapping.
ICCD
Mingyang Kou, Jun Zeng, Xinyu Peng, Weiqing Ji, Hailong Yao
2025 — conf
VAER: Via-Aware Escape Routing for Chiplet Interconnection.
ACM Great Lakes Symposium on VLSI
Haochang Tian, Weiqing Ji, Mingyang Kou, Chengkai Wang, Fei Li, Hailong Yao
2024 J jnl
Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography.
CoRR
Chengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen, Fei Li, Hailong Yao
2023 J jnl
TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mingyang Kou, Jiangyuan Gu, Hailong Yao, Shaojun Wei, Shouyi Yin
2022 A* conf
GEML: GNN-based efficient mapping method for large loop applications on CGRA.
DAC
Mingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao
2022 — conf
KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference.
ACM Great Lakes Symposium on VLSI
Jun Zeng, Mingyang Kou, Hailong Yao
2022 A* conf
NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis.
NeurIPS
Jun Zeng, Mingyang Kou, Hailong Yao
2021 J jnl
Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mingyang Kou, Pei-Yi Cheng, Jun Zeng, Tsung-Yi Ho, Kazuyoshi Takagi, Hailong Yao
2020 A* conf
TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.
DAC
Mingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin