Mingqiang Huang

31 papers A* 1A 4Misc 2Journal 15Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	Gundam: A Generalized Unified Design and Analysis Model for Matrix Multiplication on Edge. ASP-DAC Quan Cheng, Haoyuan Li, Weirong Dong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto
2025	—	`conf`	A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. CICC Quan Cheng, Qiufeng Li, Weirong Dong, Mingtao Zhang, Ruilin Zhang, Mingqiang Huang, Hao Yu, Yiyu Shi, Hiromitsu Awano, Takashi Sato, Longyang Lin, Masanori Hashimoto
2025	J	`jnl`	A 29.12-TOPS/W Vector Systolic Accelerator With NAS-Optimized DNNs in 28-nm CMOS. IEEE J. Solid State Circuits Kai Li, Mingqiang Huang, Ang Li, Shuxin Yang, Quan Cheng, Hao Yu
2025	A	`conf`	A Scalable External Memory Access and On-Chip Storage Architecture for Edge-AI Accelerators : - Multi-Path Rolling Data Refresh and Layer-Wise Bank Allocation -. ISLPED Quan Cheng, Huizi Zhang, Qiufeng Li, Yuan Liang, Mingtao Zhang, Zhenzhe Chen, Ruilin Zhang, Jinjun Xiong, Mingqiang Huang, Longyang Lin, Masanori Hashimoto
2025	J	`jnl`	A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator. CoRR Sixiao Huang, Tintin Wang, Ang Li, Ao Shen, Kai Li, Keyao Jiang, Mingqiang Huang, Hao Yu
2025	—	`conf`	An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator. ASAP Sixiao Huang, Tintin Wang, Keyao Jiang, Ao Shen, Kai Li, Ang Li, Mingqiang Huang, Hao Yu
2025	J	`jnl`	EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. IEEE Trans. Circuits Syst. I Regul. Pap. Mingqiang Huang, Ao Shen, Kai Li, Haoxiang Peng, Boyu Li, Yupeng Su, Hao Yu
2025	J	`jnl`	High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm. IEEE Trans. Circuits Syst. I Regul. Pap. Wanting Wen, Guangchao Zhao, Wanbo Hu, Ziye Li, Xingli Wang, Eby G. Friedman, Beng Kang Tay, Shaolin Ke, Mingqiang Huang
2024	—	`conf`	A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping. A-SSCC Quan Cheng, Longyang Lin, Mingqiang Huang, Qiufeng Li, Zhengke Yang, Liuyao Dai, Hao Yu, Yu-Jen Chen, Yiyu Shi, Masanori Hashimoto
2024	—	`conf`	A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS. CICC Kai Li, Hantao Huang, Mingqiang Huang, Chenchen Ding, Longyang Lin, Liebing Ni, Hao Yu
2024	J	`jnl`	EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. CoRR Mingqiang Huang, Ao Shen, Kai Li, Haoxiang Peng, Boyu Li, Hao Yu
2024	J	`jnl`	Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms. IEEE Trans. Emerg. Top. Comput. Guangchao Zhao, Zhiwei Zeng, Xingli Wang, Abdelrahman G. Qoutb, Philippe Coquet, Eby G. Friedman, Beng Kang Tay, Mingqiang Huang
2024	Misc	`conf`	LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. FCCM Shuxin Yang, Chenchen Ding, Mingqiang Huang, Kai Li, Chenghao Li, Zikun Wei, Sixiao Huang, Jingyao Dong, Liuyang Zhang, Hao Yu
2023	J	`jnl`	A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. IEEE Trans. Circuits Syst. II Express Briefs Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao, Masanori Hashimoto, Hao Yu
2023	J	`jnl`	An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge. IEEE Trans. Circuits Syst. I Regul. Pap. Mingqiang Huang, Junyi Luo, Chenchen Ding, Zikun Wei, Sixiao Huang, Hao Yu
2023	—	`conf`	Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet. AICAS Jiahao Chen, Wanbo Hu, Wenling Ma, Zhilin Zhang, Mingqiang Huang
2023	A	`conf`	Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. FPGA Mingqiang Huang, Yucen Liu, Sixiao Huang, Kai Li, Qiuping Wu, Hao Yu
2023	—	`conf`	RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach. AICAS Wenling Ma, Lianzheng Li, Ziye Li, Guangchao Zhao, Xiaojing Long, Mingqiang Huang
2023	J	`jnl`	Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Quan Cheng, Mingqiang Huang, Changhai Man, Ao Shen, Liuyao Dai, Hao Yu, Masanori Hashimoto
2022	—	`conf`	A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation. AICAS Lunshuai Pan, Peng Xue, Hongxing Li, Litao Sun, Mingqiang Huang
2022	J	`jnl`	A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Mingqiang Huang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, Hao Yu
2022	A	`conf`	A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. FPGA Mingqiang Huang, Yucen Liu, Quan Cheng, Shuxin Yang, Kai Li, Junyi Luo, Zhengke Yang, Qiufeng Li, Hao Yu, Changhai Man
2022	A	`conf`	A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge. DATE Kai Li, Junzhuo Zhou, Yuhang Wang, Junyi Luo, Zhengke Yang, Shuxin Yang, Wei Mao, Mingqiang Huang, Hao Yu
2022	J	`jnl`	An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. Dingbang Liu, Haoxiang Zhou, Wei Mao, Jun Liu, Yuliang Han, Changhai Man, Qiuping Wu, Zhiru Guo, Mingqiang Huang, Shaobo Luo, Mingsong Lv, Quan Chen, Hao Yu
2022	J	`jnl`	An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. Wei Mao, Liuyao Dai, Kai Li, Quan Cheng, Yuhang Wang, Laimin Du, Shaobo Luo, Mingqiang Huang, Hao Yu
2022	Misc	`conf`	Dual-Line-Systolic Array for High Performance CNN Accelerator. FCCM Peng Xue, Lunshuai Pan, Litao Sun, Mingqiang Huang
2021	J	`jnl`	AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence. CoRR Yunhe Wang, Mingqiang Huang, Kai Han, Hanting Chen, Wei Zhang, Chunjing Xu, Dacheng Tao
2021	J	`jnl`	Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks. Adv. Intell. Syst. Wei Zhang, Lunshuai Pan, Xuelong Yan, Guangchao Zhao, Hong Chen, Xingli Wang, Beng Kang Tay, Gaokuo Zhong, Jiangyu Li, Mingqiang Huang
2021	A*	`conf`	Winograd Algorithm for AdderNet. ICML Wenshuo Li, Hanting Chen, Mingqiang Huang, Xinghao Chen, Chunjing Xu, Yunhe Wang
2021	J	`jnl`	Winograd Algorithm for AdderNet. CoRR Wenshuo Li, Hanting Chen, Mingqiang Huang, Xinghao Chen, Chunjing Xu, Yunhe Wang
2017	—	`conf`	High performance transistors based on two dimensional materials. ASICON Mingqiang Huang, Xiong Xiong, Tiaoyang Li, Yanqing Wu