Mingche Lai

54 papers A* 2A 1B 2C 7Misc 2Journal 25Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 61.4 Gb/s/mm Wireline Transceiver Using a 7 bit-Over-8 Lane Symmetric Correlated Coding for High-Density Interconnects.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mingche Lai, Geng Zhang, Fangxu Lv, Liquan Xiao, Xuqiang Zheng, Heng Huang, Kewei Xin, Liangyong Yuan, Ruixiao Kuai, Bolin Ren, Ruotian Yin, Guohe Zhang, Chao Fan
2026 J jnl
CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yanjing Wang, Lizhou Wu, Wentao Hong, Yang Ou, Zicong Wang, Sunfeng Gao, Jie Zhang, Sheng Ma, Dezun Dong, Xingyun Qi, Mingche Lai, Nong Xiao
2026 A* conf
Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System Simulation.
HPCA
Yanjing Wang, Lizhou Wu, Sunfeng Gao, Yibo Tang, Junhui Luo, Zicong Wang, Yang Ou, Dezun Dong, Nong Xiao, Mingche Lai
2025 J jnl
A 100 Gb/s PAM4 receiver analog front-end with 33.1-dB boost in 28-nm CMOS process.
IEICE Electron. Express
Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Wenxiang Zhen, Mingche Lai, Zhi Jin, Xinyu Liu
2025 J jnl
A 112-Gb/s PAM-4 Retimer Transceiver With Jitter-Filtering Clocking Scheme and BER Optimization Technique in 28-nm CMOS.
IEEE J. Solid State Circuits
Hua Xu, Mingche Lai, Xuqiang Zheng, Zedong Wang, Jiang Xu, Sai Li, Fangxu Lv, Min Liu, Weijie Li, Zhanhao Wen, Xuan Guo, Xinhua Wang, Zhi Jin, Xinyu Liu
2025 J jnl
A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Utilizing a Complementary-Injection Scheme and an Adaptive Pulsewidth Adjustment.
IEEE J. Solid State Circuits
Zedong Wang, Xuqiang Zheng, Yu He, Hua Xu, Sai Li, Zunsong Yang, Fangxu Lv, Mingche Lai, Xinyu Liu
2025 J jnl
A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline Transceivers.
IEEE Trans. Very Large Scale Integr. Syst.
Chaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang, Zhang Luo, Shijie Li, Geng Zhang
2025 J jnl
A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver.
Microelectron. J.
Cewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai
2025 J jnl
An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline Receiver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang
2025 J jnl
CRFF: A Static Contention-Free 23T Flip-Flop With Three Clock Load Transistors for Ultra-Low-Power Applications.
IEEE J. Solid State Circuits
Kun Su, Mingche Lai, Jieyu Li, Jingkun Duan, Shi Xu, Zhang Luo, Weifeng He
2025 J jnl
Cohet: A CXL-Driven Coherent Heterogeneous Computing Framework with Hardware-Calibrated Full-System Simulation.
CoRR
Yanjing Wang, Lizhou Wu, Sunfeng Gao, Yibo Tang, Junhui Luo, Zicong Wang, Yang Ou, Dezun Dong, Nong Xiao, Mingche Lai
2025 C conf
Enhancing Transformer Inference Efficiency on FPGA Through Fully Fusion and Integer-Only Quantization Techniques.
ICCD
Zhenqi Li, Yuan Li, Mingche Lai, Puguang Liu, Qiang Wang, Yankang Zhao, Hanyuan Li, Xingyun Qi
2025 — conf
FPAMM: Fine-Grained Pipeline Architecture Accelerator for the Novel Transformer Architecture - Monarch Mixer.
ICA3PP (2)
Hanyuan Li, Mingche Lai, Xingyun Qi, Puguang Liu, Qiang Wang, Zhenqi Li, Yihang Lu, Yuan Li
2025 A conf
Late Breaking Results: AFS: Improving Accuracy of Quantized Mamba via Aggressive Forgetting Strategy.
DATE
Zhouquan Liu, Libo Huang, Ling Yang, Gang Chen, Wei Liu, Mingche Lai, Yongwen Wang
2025 — conf
Low-Cost Approximate Floating-Point Multiplier Design Based on SSA and Sparse Processing.
ICA3PP (6)
Xin Peng, Pengcheng Li, Gang Chen, Mingche Lai, Lin Deng, Qianmin Yang, Yongwen Wang, Libo Huang
2025 C conf
PIAR: Path-Improved Adaptive Routing for Dragonfly Networks.
CLUSTER
Zhenghao Wang, Qiang Wang, Mingche Lai, Jiaqing Xu, Jinbo Xu, Min Xie, Guo Chen
2025 — conf
PSCA: A FPGA-based Protein Structure Comparison Accelerator with Symmetric Simplified Matrix.
ICA3PP (6)
Hui Su, Yuan Li, Xingyun Qi, Qiang Wang, Puguang Liu, Haoyu Liao, Mingche Lai
2025 Misc conf
RISC-TAE: Instruction Set Extension for Transformer Model Acceleration.
CASES
Fei Liu, Yanping Shao, Zhouquan Liu, Jing Zhang, Junbo Tie, Mingche Lai, Gang Chen, Libo Huang
2025 — conf
Real-Time Demonstration of FPGA-Based Advanced Equalizer with ZF-NL-RSSE for Data Center Interconnects.
ECOC
Zhouhao Yang, Fangxu Lv, Mingche Lai, Zhang Luo, Weixia Xu, Chaolong Xu, Kefan Ma, Xiaoyue Hu, Cewen Liu, Zheng Peng, Xianchao Zeng
2025 Misc conf
vtism: Efficient Tiered Memory Management for Virtual Machines with CXL.
SYSTOR
Zhixing Lu, Yang Ou, Lizhou Wu, Zicong Wang, Mingche Lai, Xuran Ge, Zhenlong Song, Min Xie
2024 J jnl
A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface.
Microelectron. J.
Bolin Ren, Fangxu Lv, Mingche Lai, Liquan Xiao, Geng Zhang, Xuqiang Zheng, Zhang Luo, Jiaqing Xu
2024 J jnl
A Comprehensive Simulation Framework for CXL Disaggregated Memory.
CoRR
Yanjing Wang, Lizhou Wu, Wentao Hong, Yang Ou, Zicong Wang, Sunfeng Gao, Jie Zhang, Sheng Ma, Dezun Dong, Xingyun Qi, Mingche Lai, Nong Xiao
2024 C conf
A High-performance Hardware Accelerator for Genome Alignment.
ISPA
Haoyu Liao, Yuan Li, Qiang Wang, Mingche Lai, Hui Su, Ziwen Li, Xingyun Qi
2024 J jnl
A fully digital timing background calibration algorithm based on first-order auto-correlation for time-interleaved ADCs.
Microelectron. J.
Meng Li, Fangxu Lv, Mingche Lai, Xuqiang Zheng, Heng Huang, Xingyun Qi, Geng Zhang
2024 J jnl
A high speed and low BER dual-mode adaptive equalizer using hybrid parallel DFE.
IEICE Electron. Express
Xiaoyue Hu, Fangxu Lv, Mingche Lai, Zhang Luo, Qiang Wang, Chaolong Xu, Ruotian Yin, Zhouhao Yang, Cewen Liu
2024 — conf
A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiver.
A-SSCC
Chaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang, Liquan Xiao, Cewen Liu, Hua Xu
2024 — conf
An Injection-Locked Clock Multiplier with Adaptive Pulsewidth Adjustment and Phase Error Cancellation Achieving 43.9fs RMS Jitter and -255.5dB FoM.
CICC
Yu He, Xuqiang Zhenq, Zedong Wang, Zunsong Yanq, Hua Xu, Fangxu Lv, Mingche Lai, Xinyu Liu
2024 J jnl
Artificial Neural Network Based on Memristive Circuit for High-Speed Equalization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhang Luo, Sichun Du, Zedi Zhang, Fangxu Lv, Qinghui Hong, Mingche Lai
2024 C conf
Automatic Implementation of Large-Scale CNNs on FPGA Cluster Based on HLS4ML.
ISPA
Yihang Lu, Xingyun Qi, Yuan Li, Mingche Lai, Yankang Zhao, Zhenqi Li, Hanyuan Li, Qiang Wang
2024 J jnl
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator.
IEEE Trans. Circuits Syst. II Express Briefs
Kewei Xin, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li
2024 C conf
Optimization of TDM Using Single-ended Transmission for Multi-FPGA Platforms.
ISCAS
Haoyu Liao, Yuan Li, Puguang Liu, Qiang Wang, Mingche Lai, Xingyun Qi
2024 A* conf
Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption.
DAC
Yuxuan Qin, Chuxiong Lin, Mingche Lai, Zhang Luo, Shi Xu, Weifeng He
2023 J jnl
A 50 Gb/s PAM-4 EAM driver in 28-nm CMOS technology.
Microelectron. J.
Qiuyue Zhang, Xuqiang Zheng, Fangxu Lv, Zhaoyang Liu, Hua Xu, Weijie Li, Zhi Jin, Mingche Lai, Xinyu Liu
2023 — conf
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks.
HPCC/DSS/SmartCity/DependSys
Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu
2023 C conf
A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip.
ISCAS
Lin Shao, Mingche Lai, Shi Xu, Chuxiong Lin, Weifeng He
2023 J jnl
A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router.
IEEE Trans. Circuits Syst. II Express Briefs
Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Weifeng He
2022 J jnl
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS.
Microelectron. J.
Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi
2022 J jnl
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication.
IEEE Access
Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu
2022 J jnl
Hierarchical photoelectric hybrid packet switching network for high-performance computing.
JOCN
Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Wei-Feng He
2022 — conf
In-Band Management Framework and Performance Evaluation for Interconnect Network in the TianHe Exascale Prototype System.
HPCC/DSS/SmartCity/DependSys
Jijun Cao, Mingche Lai, Lu Liu, Jiaqing Xu, Xiaoyue Hu
2021 B conf
PFT: A Congestion Avoidance Method based on Proactive Flow Throttling at Endpoints.
IM
Xingyun Qi, Mingche Lai, Dezun Dong, Yi Dai, Junsheng Chang, Jijun Cao
2020 — conf
A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology.
ACA
Zhengbin Pang, Fangxu Lv, Weiping Tang, Mingche Lai, Kaile Guo, Yuxuan Wu, Tao Liu, Miaomiao Wu, Dechao Lu
2020 J jnl
A scalable smart router architecture with intelligent adaptive routing and fault-tolerant management.
Neurocomputing
Shi Xu, Mingche Lai, Yi Dai, Jijun Cao, Kefei Wang
2020 — conf
Design of Converged Network Coding Layer for the Ethernet and HPC High-Speed Network.
HPCC/DSS/SmartCity
Chao Wang, Weixia Xu, Mingche Lai, Jijun Cao
2020 — conf
MPLEG: A Multi-mode Physical Layer Error Generator for Link Layer Fault Tolerance Test.
ACA
Xingyun Qi, Pingjing Lu, Jijun Cao, Yi Dai, Mingche Lai, Junsheng Chang
2020 — conf
Optimal Implementation of In-Band Network Management for High-Radix Switches.
ACA
Jijun Cao, Mingche Lai, Xingyun Qi, Yi Dai, Zhengbin Pang
2019 B conf
Efficient Management and Intelligent Fault Tolerance for HPC Interconnect Networks.
ICPADS
Jijun Cao, Mingche Lai, Zhang Luo, Jiaqing Xu, Zhengbin Pang
2019 — conf
PPS: A Low-Latency and Low-Complexity Switching Architecture Based on Packet Prefetch and Arbitration Prediction.
ICA3PP (1)
Yi Dai, Ke Wu, Mingche Lai, Qiong Li, Dezun Dong
2018 J jnl
Integrated High-Speed Optical SerDes over 100GBd Based on Optical Time Division Multiplexing.
ACM J. Emerg. Technol. Comput. Syst.
Shi Xu, Zhang Luo, Mingche Lai, Zhengbin Pang, Renfa Li
2018 J jnl
Optimize the Power Consumption and SNR of the 3D Photonic High-Radix Switch Architecture Based on Extra Channels and Redundant Rings.
J. Comput. Networks Commun.
Jie Jian, Mingche Lai, Liquan Xiao
2016 J jnl
A Fast Hierarchical Arbitration in Optical Network-on-Chip Based on Multi-Level Priority QoS.
IEICE Trans. Commun.
Jie Jian, Mingche Lai, Liquan Xiao
2016 — conf
A High-Radix Switch Architecture Based on Silicon Photonic and 3D Integration.
NCCET
Jie Jian, Liquan Xiao, Mingche Lai, Shi Xu
2016 C conf
Graphein: A Novel Optical High-Radix Switch Architecture for 3D Integration.
ICA3PP
Jie Jian, Mingche Lai, Liquan Xiao, Weixia Xu
2015 — conf
A Low-Latency and High-Throughput Multiple-Level Arbitration Scheme Supporting Quality-of-Service in Optical On-chip Network.
NoCArc@MICRO
Jie Jian, Mingche Lai, Liquan Xiao