Ming Ling

69 papers A* 2A 5B 2Misc 1Journal 47Unranked 12
YearRankTypeTitle / Venue / Authors
2026 J jnl
BenDan: Benchmarking DPU performance on FPGAs.
Integr.
Han Bao, Xingyu Liu, Xiaoke Wang, Ahmed Sadaqa, Yanxiang Zhu, Shidi Tang, Ruiqi Chen, Ming Ling, Bruno da Silva
2026 J jnl
FP8ApproxLib: An FPGA-based approximate multiplier library for 8-bit floating point.
J. Syst. Archit.
Ruiqi Chen, Yangxintong Lyu, Han Bao, Shidi Tang, Jindong Li, Yanxiang Zhu, Ming Ling, Bruno da Silva
2026 J jnl
Hessian-driven N:M sparsity and quantization co-optimization for edge device deployment.
Integr.
Minghao Tang, Ming Ling, Minhua Ren, Zhihua Cai, Zhen Liu, Shidi Tang, Jianjun Li
2025 J jnl
A framework for dynamic assessment of soil erosion and detection of driving factors in alpine grassland ecosystems using the RUSLE-InVEST (SDR) model and Geodetector: A case study of the source region of the Yellow River.
Ecol. Informatics
Hucheng Li, Jianjun Chen, Ming Ling, Zizhen Chen, Yanping Lan, Qinyi Huang, Xinhong Li, Haotian You, Feng Wang, Xiaowen Han, Guoqing Zhou
2025 A conf
ATE-GCN: An FPGA-Based Graph Convolutional Network Accelerator with Asymmetrical Ternary Quantization.
DATE
Ruiqi Chen, Jiayu Liu, Shidi Tang, Yang Liu, Yanxiang Zhu, Ming Ling, Bruno da Silva
2025 J jnl
Camulator: A Lightweight and Extensible Trace-Driven Cache Simulator for Embedded Multicore SoCs.
IEEE Comput. Archit. Lett.
Yuhan Liu, Zihang Yang, Fei Tong, Liang Cheng, Ming Ling
2025 — conf
D-GCN: A Dynamic Pruning Accelerator for Deep Graph Convolutional Networks with Hybrid Dataflow.
ACM Great Lakes Symposium on VLSI
Shun Li, Hao Zhou, Enhao Tang, Yang Liu, Shidi Tang, Ming Ling
2025 A conf
Diff-DiT: Temporal Differential Accelerator for Low-bit Diffusion Transformers on FPGA.
ICCAD
Shidi Tang, Pengwei Zheng, Ruiqi Chen, Yuxuan Lv, Bruno da Silva, Ming Ling
2025 — conf
DiffDock-FPGA: A Hardware Accelerator for Molecular Docking with Customized Tensor Product Framework and Sparse-Aware Access Strategy.
ACM Great Lakes Symposium on VLSI
Chuanzhao Zhang, Rui Liu, Shidi Tang, Shun Li, Ming Ling
2025 J jnl
EEVS: Redeploying Discarded Smartphones for Economic and Ecological Drug Molecules Virtual Screening.
IEEE Trans. Sustain. Comput.
Ming Ling, Chuanzhao Zhang, Shidi Tang, Ruiqi Chen, Yanxiang Zhu
2025 Misc conf
FPGA-Based Approximate Multiplier for FP8.
FCCM
Ruiqi Chen, Yangxintong Lyu, Han Bao, Jiayu Liu, Yanxiang Zhu, Shidi Tang, Ming Ling, Bruno da Silva
2025 J jnl
PULP-Lite: a more light-weighted multi-core framework for IoT applications.
Int. J. Sens. Networks
Yong Yang, Yuyu Lian, Yanxiang Zhu, Shun Li, Wenhua Gu, Ming Ling
2025 J jnl
Pixel-Based Clustering for Local Interpretable Model-Agnostic Explanations.
J. Artif. Intell. Soft Comput. Res.
Junyan Qian, Tong Wen, Ming Ling, Xiaofu Du, Hao Ding
2025 J jnl
Vina-FPGA2: a high-level parallelized hardware-accelerated molecular docking tool based on the inter-module pipeline.
Frontiers Inf. Technol. Electron. Eng.
Ming Ling, Shidi Tang, Ruiqi Chen, Xin Li, Yanxiang Zhu
2024 J jnl
An improved point cloud denoising method in adverse weather conditions based on PP-LiteSeg network.
PeerJ Comput. Sci.
Wenzhen Zhang, Ming Ling
2024 J jnl
Evaluation of driving effects of carbon storage change in the source of the Yellow River: A perspective with CMIP6 future development scenarios.
Ecol. Informatics
Ming Ling, Zihao Feng, Zizhen Chen, Yanping Lan, Xinhong Li, Haotian You, Xiaowen Han, Jianjun Chen
2024 J jnl
Explainable machine learning-based fractional vegetation cover inversion and performance optimization - A case study of an alpine grassland on the Qinghai-Tibet Plateau.
Ecol. Informatics
Xinhong Li, Jianjun Chen, Zizhen Chen, Yanping Lan, Ming Ling, Qinyi Huang, Hucheng Li, Xiaowen Han, Shuhua Yi
2024 J jnl
Fatigue life prediction driven by mesoscopic defect data.
Eng. Appl. Artif. Intell.
Chao Wang, Yali Yang, Hao Chen, Sha Xu, Yongfang Li, Ruoping Zhang, Ming Ling
2024 — conf
Modeling Equivariant Neural Networks for Hardware Acceleration, a Case Study on the Molecular Docking Tool DiffDock.
PACRIM
Shidi Tang, Xingxing Zhou, Ming Ling
2024 J jnl
PCG: Mitigating Conflict-based Cache Side-channel Attacks with Prefetching.
CoRR
Fang Jiang, Fei Tong, Hongyu Wang, Xiaoyu Cheng, Zhe Zhou, Ming Ling, Yuxing Mao
2024 J jnl
Preventing short violations in clock routing with an SVM classifier before powerplanning and placement.
Microelectron. J.
Qi Liu, Ming Ling, Yanxiang Zhu, Yibo Rui, Rui Wang
2024 — conf
Project-Based Analog Circuit Experiment Design for Lane Detection and Tracking in Electric Trolley Systems.
TALE
Zheng Lei, Renjie Hu, Fenghua Wang, Wei Wang, Xuejiao Tang, Ming Ling
2024 J jnl
Tradeoffs among multi-source remote sensing images, spatial resolution, and accuracy for the classification of wetland plant species and surface objects based on the MRS_DeepLabV3+ model.
Ecol. Informatics
Zizhen Chen, Jianjun Chen, Yuemin Yue, Yanping Lan, Ming Ling, Xinhong Li, Haotian You, Xiaowen Han, Guoqing Zhou
2024 J jnl
Ultra8T: A sub-threshold 8T SRAM with leakage detection.
Integr.
Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu
2024 J jnl
Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool With High-Accuracy and Multi-Level Parallelism.
IEEE Trans. Biomed. Circuits Syst.
Ming Ling, Zhihao Feng, Ruiqi Chen, Yi Shao, Shidi Tang, Yanxiang Zhu
2023 — conf
A New Process Framework for Managing the Fuzzy Front End of New Healthcare Device Development.
HCI (24)
Fan Yang, Zheng Qing, Ming Ling, Wa An
2023 A conf
A Novel Delay Calibration Method Considering Interaction between Cells and Wires.
DATE
Leilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi
2023 J jnl
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shan Shen, Peng Cao, Ming Ling, Longxing Shi
2023 J jnl
Effectiveness Analysis of Multiple Initial States Simulated Annealing Algorithm, a Case Study on the Molecular Docking Tool AutoDock Vina.
IEEE ACM Trans. Comput. Biol. Bioinform.
Xingxing Zhou, Ming Ling, Qingde Lin, Shidi Tang, Jiansheng Wu, Haifeng Hu
2023 J jnl
FemtoDet: An Object Detection Baseline for Energy Versus Performance Tradeoffs.
CoRR
Peng Tu, Xu Xie, Ming Ling, Min Yang, Guo Ai, Yawen Huang, Yefeng Zheng
2023 J jnl
Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection.
CoRR
Shan Shen, Hao Xu, Yongliang Zhou, Ming Ling, Wenjian Yu
2023 J jnl
Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism.
IEEE Trans. Very Large Scale Integr. Syst.
Ming Ling, Qingde Lin, Ruiqi Chen, Haimeng Qi, Mengru Lin, Yanxiang Zhu, Jiansheng Wu
2023 J jnl
Vina-GPU 2.0: Further Accelerating AutoDock Vina and Its Derivatives with Graphics Processing Units.
J. Chem. Inf. Model.
Ji Ding, Shidi Tang, Zheming Mei, Lingyue Wang, Qinqin Huang, Haifeng Hu, Ming Ling, Jiansheng Wu
2022 J jnl
A Fast Cross-Layer Dynamic Power Estimation Method by Tracking Cycle-Accurate Activity Factors With Spark Streaming.
IEEE Trans. Very Large Scale Integr. Syst.
Leilei Jin, Wenjie Fu, Ming Ling, Longxing Shi
2022 J jnl
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools.
IEEE Embed. Syst. Lett.
Ming Ling, Hongxi Li, Xiang Yu
2022 J jnl
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model.
CoRR
Shan Shen, Peng Cao, Ming Ling, Longxing Shi
2021 J jnl
A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages.
IEEE Trans. Very Large Scale Integr. Syst.
Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang
2021 J jnl
Analytical Modeling the Multi-Core Shared Cache Behavior With Considerations of Data-Sharing and Coherence.
IEEE Access
Ming Ling, Xiaoqian Lu, Guangmin Wang, Jiancong Ge
2021 J jnl
Dual fluoroscopic imaging and CT-based finite element modelling to estimate forces and stresses of grafts in anatomical single-bundle ACL reconstruction with different femoral tunnels.
Int. J. Comput. Assist. Radiol. Surg.
Yang Xiao, Ming Ling, Zhenming Liang, Jian Ding, Shi Zhan, Hai Hu, Bin Chen
2020 A* conf
A Cross-Layer Power and Timing Evaluation Method for Wide Voltage Scaling.
DAC
Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi
2020 J jnl
AMPS: Accelerating McPAT Power Evaluation Without Cycle-Accurate Simulations.
IEEE Embed. Syst. Lett.
Wenjie Fu, Ming Ling, Wei Wang, Longxing Shi
2020 J jnl
Analytical Modeling the Multi-Core Shared Cache Behavior with Considerations of Data-Sharing and Coherence.
CoRR
Ming Ling, Guangmin Wang, Jiancong Ge, Xiaoqian Lu
2020 J jnl
Fast modeling L2 cache reuse distance histograms using combined locality information from software traces.
J. Syst. Archit.
Ming Ling, Jiancong Ge, Guangmin Wang
2020 J jnl
Mapping-Based Dosage of Gait Modification Selection for Multi-Parameter, Subject-Specific Gait Retraining.
IEEE Access
Junkai Xu, Fangyuan Cao, Shi Zhan, Ming Ling, Hai Hu, Peter B. Shull
2020 A conf
Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAM.
DATE
Shan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi
2020 J jnl
TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages.
IEEE Trans. Very Large Scale Integr. Syst.
Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi
2020 A* conf
TYMER: A Yield-based Performance Model for Timing-speculation SRAM.
DAC
Shan Shen, Liang Pang, Tianxiang Shao, Ming Ling, Xiao Shi, Longxing Shi
2020 J jnl
VASTA: A Wide Voltage Statistical Timing Analysis Tool Based on Variation-Aware Cell Delay Models.
IEEE Access
Wenjie Fu, Leilei Jin, Ming Ling, Yu Zheng, Longxing Shi
2019 B conf
A Data-Sharing Aware and Scalable Cache Miss Rates Model for Multi-Core Processors with Multi-Level Cache Hierarchies.
ICPADS
Guangmin Wang, Jiancong Ge, Yunhao Yan, Ming Ling
2019 — conf
A Fast Reduction Method for Path Process Variations Without Time-Consuming Training.
ASICON
Wenjie Fu, Yu Zheng, Leilei Jin, Ming Ling
2019 — conf
Accelerating the Analytical Modeling of Memory Level Parallelism by the Probability Analysis.
PACRIM
Yunhao Yan, Ming Ling
2019 J jnl
An Active Mobile Charging and Data Collection Scheme for Clustered Sensor Networks.
IEEE Trans. Veh. Technol.
Kaiyang Liu, Jun Peng, Liang He, Jianping Pan, Shuo Li, Ming Ling, Zhiwu Huang
2019 J jnl
An embedded implementation of CNN-based hand detection and orientation estimation algorithm.
Mach. Vis. Appl.
Li Yang, Zhi Qi, Zeheng Liu, Hao Liu, Ming Ling, Longxing Shi, Xinning Liu
2019 — conf
Does the ISA Really Matter? A Simulation Based Investigation.
PACRIM
Ming Ling, Xin Xu, Yushen Gu, Zhihua Pan
2019 J jnl
Fast Modeling L2 Cache Reuse Distance Histograms Using Combined Locality Information from Software Traces.
CoRR
Ming Ling, Jiancong Ge, Guangmin Wang
2019 B conf
Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces.
ISPASS
Jiancong Ge, Ming Ling
2019 J jnl
Fast modeling DRAM access latency based on the LLC memory stride distribution without detailed simulations.
Microprocess. Microsystems
Ming Ling, Xiaojing Shang, Kecheng Ji, Longxing Shi
2019 J jnl
Lowering the Hit Latencies of Low Voltage Caches Based on the Cross-Sensing Timing Speculation SRAM.
IEEE Access
Ming Ling, Xiaojing Shang, Shan Shen, Tianxiang Shao, Jun Yang
2019 — conf
RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanism.
MEMSYS
Xiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang
2019 J jnl
TS Cache: A Fast Cache with Timing-speculation Mechanism Under Low Supply Voltages.
CoRR
Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang, Longxing Shi
2018 J jnl
An Analytical Cache Performance Evaluation Framework for Embedded Out-of-Order Processors Using Software Characteristics.
ACM Trans. Embed. Comput. Syst.
Kecheng Ji, Ming Ling, Longxing Shi, Jianping Pan
2018 J jnl
Detecting the phase behavior on cache performance using the reuse distance vectors.
J. Syst. Archit.
Shan Shen, Ming Ling, Yongtao Zhang, Longxing Shi
2017 — conf
A mechanistic model of memory level parallelism fed with cache miss rates.
PACRIM
Qin Wang, Kecheng Ji, Ming Ling, Longxing Shi
2017 — conf
A trace-driven analytical model with less profiling overhead for DRAM access latencies.
PACRIM
Fengying Sun, Kecheng Ji, Ming Ling, Longxing Shi
2017 A conf
AFEC: An analytical framework for evaluating cache performance in out-of-order processors.
DATE
Kecheng Ji, Ming Ling, Qin Wang, Longxing Shi, Jianping Pan
2017 J jnl
An artificial neural network model of LRU-cache misses on out-of-order embedded processors.
Microprocess. Microsystems
Kecheng Ji, Ming Ling, Yang Zhang, Longxing Shi
2017 J jnl
Using the first-level cache stack distance histograms to predict multi-level LRU cache misses.
Microprocess. Microsystems
Kecheng Ji, Ming Ling, Longxing Shi
2013 — conf
A novel energy-oriented reconfigurable on-chip unified memory architecture based on Cache Behavior Phase Graph.
ASICON
Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang
2012 J jnl
Dynamic Allocation of SPM Based on Time-Slotted Cache Conflict Graph for System Optimization.
IEICE Trans. Inf. Syst.
Jianping Wu, Ming Ling, Yang Zhang, Chen Mei, Huan Wang