| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2006 | — | conf |
ICIC (2)
|
| 2006 | J | jnl |
Boosting SMT trace processors performance with data cache misssensitive thread scheduling mechanism.
Microprocess. Microsystems
|
| 2006 | J | jnl |
Microprocess. Microsystems
|
| 2006 | — | conf |
ISPA Workshops
|
| 2005 | — | conf |
ITCC (2)
|
| 2005 | — | conf |
WAIM
|
| 2005 | — | conf |
ITCC (2)
|
| 2005 | J | jnl |
J. Comput. Sci. Technol.
|
| 2004 | — | conf |
ESA/VLSI
|
| 2004 | — | conf |
PCM (3)
|
| 2004 | — | conf |
PCM (3)
|
| 2004 | — | conf |
IWSOC
|
| 1988 | — | conf |
DS-3
|