Ming-Shuan Chen

11 papers Journal 5Unranked 6
YearRankTypeTitle / Venue / Authors
2015 J jnl
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology.
IEEE J. Solid State Circuits
Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
2015 J jnl
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology.
IEEE J. Solid State Circuits
Ming-Shuan Chen, Chih-Kong Ken Yang
2015 — conf
A low-PDP and low-area repeater using passive CTLE for on-chip interconnects.
VLSIC
Ming-Shuan Chen, Mau-Chung Frank Chang, Chih-Kong Ken Yang
2014 — conf
A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS.
CICC
Ming-Shuan Chen, Chih-Kong Ken Yang
2013 J jnl
A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection.
IEEE J. Solid State Circuits
Ming-Shuan Chen, Amr Amin Hafez, Chih-Kong Ken Yang
2013 — conf
A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS.
ISSCC
Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
2012 J jnl
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology.
IEEE J. Solid State Circuits
Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
2012 — conf
A low-power highly multiplexed parallel PRBS generator.
CICC
Ming-Shuan Chen, Chih-Kong Ken Yang
2011 — conf
A 40Gb/s TX and RX chip set in 65nm CMOS.
ISSCC
Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
2008 — conf
A 20Gb/s Duobinary Transceiver in 90nm CMOS.
ISSCC
Jri Lee, Ming-Shuan Chen, Huaide Wang
2008 J jnl
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data.
IEEE J. Solid State Circuits
Jri Lee, Ming-Shuan Chen, Huaide Wang