Ming-Jer Kao

12 papers A 3Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2015 J jnl
Set-Triggered-Parallel-Reset Memristor Logic for High-Density Heterogeneous-Integration Friendly Normally Off Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Meng-Fan Chang, Shu-Meng Yang, Chia-Chen Kuo, Ting-Chin Yang, Che-Ju Yeh, Tun-Fei Chien, Li-Yue Huang, Shyh-Shyuan Sheu, Pei-Ling Tseng, Yu-Sheng Chen, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
2014 — conf
A nonvolatile look-up table using ReRAM for reconfigurable logic.
A-SSCC
Wen-Pin Lin, Shyh-Shyuan Sheu, Chia-Chen Kuo, Pei-Ling Tseng, Meng-Fan Chang, Keng-Li Su, Chih-Sheng Lin, Kan-Hsueh Tsai, Sih-Han Lee, Szu-Chieh Liu, Yu-Sheng Chen, Heng-Yuan Lee, Ching-Chih Hsu, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
2014 — conf
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing.
VLSIC
Li-Yue Huang, Meng-Fan Chang, Ching-Hao Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Keng-Li Su, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao
2013 J jnl
A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes.
IEEE J. Solid State Circuits
Meng-Fan Chang, Shyh-Shyuan Sheu, Ku-Feng Lin, Che-Wei Wu, Chia-Chen Kuo, Pi-Feng Chiu, Yih-Shan Yang, Yu-Sheng Chen, Heng-Yuan Lee, Chen-Hsin Lien, Frederick T. Chen, Keng-Li Su, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
2013 — conf
Challenges of Cu CMP of TSVs and RDLs fabricated from the backside of a thin wafer.
3DIC
Jui-Chin Chen, John H. Lau, Tzu-Chien Hsu, Chien-Chou Chen, Pei-Jer Tzeng, Po-Chih Chang, Chun-Hsien Chien, Yiu-Hsiang Chang, Shang-Chun Chen, Yu-Chen Hsin, Sue-Chen Liao, Cha-Hsin Lin, Tzu-Kun Ku, Ming-Jer Kao
2011 — conf
A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability.
ISSCC
Shyh-Shyuan Sheu, Meng-Fan Chang, Ku-Feng Lin, Che-Wei Wu, Yu-Sheng Chen, Pi-Feng Chiu, Chia-Chen Kuo, Yih-Shan Yang, Pei-Chia Chiang, Wen-Pin Lin, Che-He Lin, Heng-Yuan Lee, Peiyi Gu, Sumin Wang, Frederick T. Chen, Keng-Li Su, Chen-Hsin Lien, Kuo-Hsing Cheng, Hsin-Tun Wu, Tzu-Kun Ku, Ming-Jer Kao, Ming-Jinn Tsai
2010 J jnl
Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2010 J jnl
Low power design of phase-change memory based on a comprehensive model.
IET Comput. Digit. Tech.
Meng-Hsueh Chiang, Yi-Bo Liao, Jun-Tin Lin, Wei-Chou Hsu, Chu Yu, Pei-Chia Chiang, Y.-Y. Hsu, W.-H. Liu, Shyh-Shyuan Sheu, Keng-Li Su, Ming-Jer Kao, Ming-Jinn Tsai
2008 J jnl
Write Disturbance Modeling and Testing for MRAM.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ding-Yeong Wang, Yuan-Jen Lee, Ming-Jer Kao
2007 A conf
Diagnosis for MRAM write disturbance fault.
ITC
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2006 A conf
Testing MRAM for Write Disturbance Fault.
ITC
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Chien-Chung Hung, Young-Shying Chen, Ming-Jer Kao
2004 A conf
MRAM Defect Analysis and Fault Modeli.
ITC
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu