Ming-Dou Ker

193 papers C 23Misc 1Journal 87Unranked 82
YearRankTypeTitle / Venue / Authors
2025 C conf
Design of Linear Battery Charger with Self-Blocking Reverse Current Path for Biomedical Applications.
ISCAS
Wen-Hsiang Huang, Ming-Dou Ker
2025 — conf
Improved Layout Style on Diode- Trigger SCR for Low-C ESD Protection.
IRPS
Chen-Yu Liang, Ming-Dou Ker
2025 — conf
Latch-Up Over-Current Protection Design with Power Restarted Function.
IRPS
Shih-Cheng Huang, Ming-Dou Ker
2025 C conf
Miniaturized Wirelessly-Powered Biphasic Current Stimulator for Implantable Neurostimulation.
ISCAS
Chang-Chun Yang, Ming-Dou Ker
2025 C conf
SDLA-based Logarithmic Amplifier Integrated with Magnitude Discriminator and Time Discriminator for Real-Time ESD Event Detection.
ISCAS
Chang-Jiun Lai, Ming-Dou Ker
2024 C conf
A Versatile 8-Channel High Voltage Stimulator for Comprehensive Neural Stimulation.
ISCAS
Kuan-Ting Lin, Ming-Dou Ker
2024 J jnl
Design of CMOS Analog Front-End Local-Field Potential Chopper Amplifier With Stimulation Artifact Tolerance for Real-Time Closed-Loop Deep Brain Stimulation SoC Applications.
IEEE Trans. Biomed. Circuits Syst.
Chung-Yu Wu, Chi-Wei Huang, Yu-Wei Chen, Chin-Kai Lai, Chung-Chih Hung, Ming-Dou Ker
2024 — conf
Embedded Deep-Nwell Collector Used to Improve Latch-Up Immunity of Multi-Functional I/O Buffer with Indirect Power-Connected N-Well.
IRPS
Chen-Wei Hsu, Ming-Dou Ker, Ping-Lin Chung, Chin-Tung Cheng, Chih-Ping Chen
2024 J jnl
Stimulation-Induced Artifact Removal of the Local Field Potential Through Hardware Design: Toward the Implantable Closed-Loop Deep Brain Stimulation.
IEEE Access
Yi-Hui Wu, Hsiao-Chun Lin, Chi-Wei Huang, Chung-Yu Wu, Ming-Dou Ker
2023 J jnl
A CMOS Synchronized Sample-and-Hold Artifact Blanking Analog Front-End Local Field Potential Acquisition Unit With ±3.6-V Stimulation Artifact Tolerance and Monopolar Electrode-Tissue Impedance Measurement Circuit for Closed-Loop Deep Brain Stimulation SoCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chi-Wei Huang, Chin-Kai Lai, Chung-Chih Hung, Chung-Yu Wu, Ming-Dou Ker
2023 J jnl
Design of Dual-Configuration Dual-Mode Stimulator in Low-Voltage CMOS Process for Neuro-Modulation.
IEEE Trans. Biomed. Circuits Syst.
Chia-Chi Hsieh, Yi-Hui Wu, Ming-Dou Ker
2023 — conf
Investigation of Safe Operating Area on 4H-SiC 600V VDMOSFET with TLP and UIS Test Methods.
IRPS
Chao-Yang Ke, Yu-Chia Tsui, Bing-Yue Tsui, Ming-Dou Ker
2022 — conf
Single Chip of Electrostatic Discharge Detector for IC Manufacturing Field Control.
VLSI-DAT
I-Hsuan Wu, Ming-Dou Ker
2021 — conf
Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit Against False Trigger During Fast Power-ON Events.
VLSI-DAT
Han-Sheng Huang, Ming-Dou Ker
2021 J jnl
Design of a Bone-Guided Cochlear Implant Microsystem With Monopolar Biphasic Multiple Stimulations and Evoked Compound Action Potential Acquisition and Its In Vivo Verification.
IEEE J. Solid State Circuits
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Li-Yang Tang, Yen-Fu Tu, Po-Chih Chang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2021 J jnl
Monopolar Biphasic Stimulator With Discharge Function and Negative Level Shifter for Neuromodulation SoC Integration in Low-Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst.
Chia-Chi Hsieh, Ming-Dou Ker
2021 Misc conf
ROT-Harris: A Dynamic Approach to Asynchronous Interest Point Detection.
MVA
Shane Harrigan, Sonya A. Coleman, Ming-Dou Ker, Pratheepan Yogarajah, Zheng Fang, Chengdong Wu
2021 — conf
Study on the Guard Rings for Latchup Prevention between HV-PMOS and LV-PMOS in a 0.15-µm BCD Process.
IRPS
Chao-Yang Chen, Jian-Hsing Lee, Karuna Nidhi, Tzer-Yaa Bin, Geeng-Lih Lin, Ming-Dou Ker
2020 J jnl
Design of Dual-Mode Stimulus Chip With Built-In High Voltage Generator for Biomedical Applications.
IEEE Trans. Biomed. Circuits Syst.
Ting-Yang Yen, Ming-Dou Ker
2020 J jnl
Design of Stage-Selective Negative Voltage Generator to Improve On-Chip Power Conversion Efficiency for Neuron Stimulation.
IEEE Trans. Circuits Syst.
Shiau-Pin Lin, Ming-Dou Ker
2020 — conf
Improved Design and In Vivo Animal Tests of Bone-Guided Cochlear Implant Microsystem with Monopolar Biphasic Multiple Stimulation and Neural Action Potential Acquisition.
A-SSCC
Sung-Hao Wang, Yu-Kai Huang, Ching-Yuan Chen, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2020 — conf
Miniaturized Intracerebral Potential Recorder for Long-Term Local Field Potential of Deep Brain Signals.
EMBC
Yi-Hui Wu, Yi-Huan Ou-Yang, Chiung-Chu Chen, Chen-Yi Lee, Chung-Yu Wu, Ming-Dou Ker
2020 — conf
Over-Voltage Protection on the CC Pin of USB Type-C Interface against Electrical Overstress Events.
IRPS
Chao-Yang Ke, Ming-Dou Ker
2019 J jnl
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Chi-Wei Liu, Yi-Lun Chen, Pei-Chun Liao, Shiau-Pin Lin, Ting-Wei Wang, Ming-Jie Chung, Po-Hung Chen, Ming-Dou Ker, Chung-Yu Wu
2019 J jnl
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhicong Luo, Li-Chin Yu, Ming-Dou Ker
2019 J jnl
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.
IEEE Trans. Biomed. Eng.
Xin-Hong Qian, Yi-Chung Wu, Tzu-Yi Yang, Cheng-Hsiang Cheng, Hsing-Chien Chu, Wan-Hsueh Cheng, Ting-Yang Yen, Tzu-Han Lin, Yung-Jen Lin, Yu-Chi Lee, Jia-Heng Chang, Shih-Ting Lin, Shang-Hsuan Li, Tsung-Chen Wu, Chien-Chang Huang, Sung-Hao Wang, Chia-Fone Lee, Chia-Hsiang Yang, Chung-Chih Hung, Tai-Shih Chi, Chien-Hao Liu, Ming-Dou Ker, Chung-Yu Wu
2019 C conf
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications.
ISCAS
Tao-Yi Hung, Ming-Dou Ker
2019 J jnl
Guest Editorial: Special Issue on Selected Papers From IEEE ISCAS 2019.
IEEE Trans. Biomed. Circuits Syst.
Ming-Dou Ker, Maurizio Valle, Matthew L. Johnston
2019 — conf
Investigation on Latch-Up Path Between I/O PMOS and Core PMOS in a 0.18-μm CMOS Process.
IRPS
Chun-cheng Chen, Ming-Dou Ker
2018 J jnl
A Fully Integrated 16-Channel Closed-Loop Neural-Prosthetic CMOS SoC With Wireless Power and Bidirectional Data Telemetry for Real-Time Efficient Human Epileptic Seizure Control.
IEEE J. Solid State Circuits
Cheng-Hsiang Cheng, Ping-Yuan Tsai, Tzu-Yi Yang, Wan-Hsueh Cheng, Ting-Yang Yen, Zhicong Luo, Xin-Hong Qian, Zhi-Xin Chen, Tzu-Han Lin, Wei-Hong Chen, Wei-Ming Chen, Sheng-Fu Liang, Fu-Zen Shaw, Cheng-Siu Chang, Yue-Loong Hsin, Chen-Yi Lee, Ming-Dou Ker, Chung-Yu Wu
2018 J jnl
A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Zhicong Luo, Ming-Dou Ker
2018 — conf
Design of Multi-Channel Monopolar Biphasic Stimulator for Implantable Biomedical Applications.
MWSCAS
Chia-Chi Hsieh, Ming-Dou Ker
2018 — conf
Design of Multiple-Charge-Pump System for Implantable Biomedical Applications.
BioCAS
Shiau-Pin Lin, Ming-Dou Ker
2018 J jnl
Surge protection design with surge-to-digital converter for microelectronic circuits and systems.
Microelectron. Reliab.
Wen-Chieh Chen, Ming-Dou Ker
2017 J jnl
A 8 Phases 192MHz Crystal-Less Clock Generator with PVT Calibration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Jen-Chieh Liu, Yu Lee
2017 J jnl
A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- μm 1.8-V/3.3-V Low-Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst.
Zhicong Luo, Ming-Dou Ker, Tzu-Yi Yang, Wan-Hsueh Cheng
2017 J jnl
An Ultra-Low Voltage CMOS Voltage Controlled Oscillator with Process and Temperature Compensation.
IEICE Trans. Electron.
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan
2017 — conf
Design considerations and clinical applications of closed-loop neural disorder control SoCs.
ASP-DAC
Chung-Yu Wu, Cheng-Hsiang Cheng, Yi-Huan Ou-Yang, Chiung-Ghu Chen, Wei-Ming Chen, Ming-Dou Ker, Chen-Yi Lee, Sheng-Fu Liang, Fu-Zen Shaw
2017 J jnl
Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process.
Microelectron. Reliab.
Chun-Yu Lin, Rui-Hong Liu, Ming-Dou Ker
2017 J jnl
Regulated Charge Pump With New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhicong Luo, Ming-Dou Ker, Wan-Hsueh Cheng, Ting-Yang Yen
2016 J jnl
A High-Voltage-Tolerant and Precise Charge-Balanced Neuro-Stimulator in Low Voltage CMOS Process.
IEEE Trans. Biomed. Circuits Syst.
Zhicong Luo, Ming-Dou Ker
2016 — conf
Design of high-voltage-tolerant level shifter in low voltage CMOS process for neuro stimulator.
NEWCAS
Zhicong Luo, Ming-Dou Ker
2016 — conf
ESD protection design for high-speed applications in CMOS technology.
MWSCAS
Jie-Ting Chen, Chun-Yu Lin, Rong-Kun Chang, Ming-Dou Ker, Tzu-Chien Tzeng, Tzu-Chiang Lin
2015 — conf
Active ESD protection for input transistors in a 40-nm CMOS process.
VLSI-DAT
Federico A. Altolaguirre, Ming-Dou Ker
2015 — conf
Compensation circuit with additional junction sensor to enhance latchup immunity for CMOS integrated circuits.
ECCTD
Hui-Wen Tsai, Ming-Dou Ker
2015 — conf
ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC.
SoCC
Chia-Tsen Dai, Ming-Dou Ker
2015 — conf
Impact of guard ring layout on the stacked low-voltage PMOS for high-voltage ESD protection.
ECCTD
Seian-Feng Liao, Kai-Neng Tang, Ming-Dou Ker, Jia-Rong Yeh, Hwa-Chyi Chiou, Yeh-Jen Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin
2014 J jnl
A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control.
IEEE J. Solid State Circuits
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Yue-Loong Hsin, Sheng-Fu Liang, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Chung-Yu Wu
2014 C conf
A high-voltage-tolerant stimulator realized in the low-voltage CMOS process for cochlear implant.
ISCAS
Kuan-Yu Lin, Ming-Dou Ker, Chun-Yu Lin
2014 C conf
ESD protection design for wideband RF applications in 65-nm CMOS process.
ISCAS
Li-Wei Chu, Chun-Yu Lin, Ming-Dou Ker, Ming-Hsiang Song, Jeng-Chou Tseng, Chewnpu Jou, Ming-Hsien Tsai
2014 J jnl
Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit.
Microelectron. Reliab.
Po-Yen Chiu, Ming-Dou Ker
2014 J jnl
On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection.
IEEE Trans. Ind. Electron.
Che-Hao Chuang, Ming-Dou Ker
2014 — conf
Power-rail ESD clamp circuit with embedded-trigger SCR device in a 65-nm CMOS process.
MWSCAS
Federico A. Altolaguirre, Ming-Dou Ker
2014 J jnl
SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance.
Microelectron. Reliab.
Ming-Dou Ker, Wan-Yen Lin, Cheng-Cheng Yen
2013 — conf
A fully integrated 8-channel closed-loop neural-prosthetic SoC for real-time epileptic seizure control.
ISSCC
Wei-Ming Chen, Herming Chiueh, Tsan-Jieh Chen, Chia-Lun Ho, Chi Jeng, Shun-Ting Chang, Ming-Dou Ker, Chun-Yu Lin, Ya-Chun Huang, Chia-Wei Chou, Tsun-Yuan Fan, Ming-Seng Cheng, Sheng-Fu Liang, Tzu-Chieh Chien, Sih-Yen Wu, Yu-Lin Wang, Fu-Zen Shaw, Yu-Hsing Huang, Chia-Hsiang Yang, Jin-Chern Chiou, Chih-Wei Chang, Lei-Chun Chou, Chung-Yu Wu
2013 — conf
Analysis and solution to overcome EOS failure induced by latchup test in a high-voltage integrated circuits.
VLSI-DAT
Hui-Wen Tsai, Ming-Dou Ker, Yi-sheng Liu, Ming-Nan Chuang
2013 — conf
Area-efficient power-rail ESD clamp circuit with SCR device embedded into ESD-transient detection circuit in a 65nm CMOS process.
VLSI-DAT
Chih-Ting Yeh, Ming-Dou Ker
2013 J jnl
Design of 2 × V
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Dou Ker, Po-Yen Chiu
2013 — conf
Design of 2×VDD logic gates with only 1×VDD devices in nanoscale CMOS technology.
SoCC
Po-Yen Chiu, Ming-Dou Ker
2013 J jnl
Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability.
IEEE Trans. Biomed. Circuits Syst.
Chun-Yu Lin, Wei-Ling Chen, Ming-Dou Ker
2013 C conf
Low-leakage power-rail ESD clamp circuit with gated current mirror in a 65-nm CMOS technology.
ISCAS
Federico A. Altolaguirre, Ming-Dou Ker
2013 J jnl
PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit.
Microelectron. Reliab.
Chih-Ting Yeh, Ming-Dou Ker
2013 — conf
Ultra-low-leakage power-rail ESD clamp circuit in a 65-nm CMOS technology.
VLSI-DAT
Federico A. Altolaguirre, Ming-Dou Ker
2012 C conf
Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology.
ISCAS
Li-Wei Chu, Chun-Yu Lin, Shiang-Yu Tsai, Ming-Dou Ker, Ming-Hsiang Song, Chewnpu Jou, Tse-Hua Lu, Jeng-Chou Tseng, Ming-Hsien Tsai, Tsun-Lai Hsu, Ping-Fang Hung, Tzu-Heng Chang
2012 — conf
Design of ESD protection for RF CMOS power amplifier with inductor in matching network.
APCCAS
Shiang-Yu Tsai, Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker
2012 — conf
Design of negative high voltage generator for biphasic stimulator with soc integration consideration.
BioCAS
Ya-Chun Huang, Ming-Dou Ker, Chun-Yu Lin
2012 — conf
High-voltage-tolerant stimulator with adaptive loading consideration for electronic epilepsy prosthetic SoC in a 0.18-µm CMOS process.
NEWCAS
Chun-Yu Lin, Yi-Ju Li, Ming-Dou Ker
2012 J jnl
Investigation on CDM ESD events at core circuits in a 65-nm CMOS process.
Microelectron. Reliab.
Chun-Yu Lin, Tang-Long Chang, Ming-Dou Ker
2012 — conf
Live demonstration: Implantable stimulator for epileptic seizure suppression with loading impedance adaptability.
BioCAS
Ming-Dou Ker, Wei-Ling Chen, Chun-Yu Lin
2012 J jnl
New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels.
IEEE Trans. Ind. Electron.
Ming-Dou Ker, Cheng-Cheng Yen
2012 J jnl
New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs
Chih-Ting Yeh, Ming-Dou Ker
2012 — conf
New design of transient-noise detection circuit with SCR device for system-level ESD protection.
NEWCAS
Ming-Dou Ker, Wan-Yen Lin
2012 — conf
New design on 2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65nm CMOS process.
VLSI-DAT
Chih-Ting Yeh, Ming-Dou Ker
2012 J jnl
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications.
Microelectron. Reliab.
Chih-Ting Yeh, Ming-Dou Ker
2011 J jnl
Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process.
Microelectron. Reliab.
Chun-Yu Lin, Li-Wei Chu, Ming-Dou Ker
2011 C conf
Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.
ISCAS
Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker
2011 J jnl
Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process.
Microelectron. Reliab.
Yi-Hsin Weng, Hui-Wen Tsai, Ming-Dou Ker
2011 J jnl
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs.
IEEE J. Solid State Circuits
Ming-Dou Ker, Wen-Yi Chen, Wuu-Trong Shieh, I-Ju Wei
2011 — conf
Modified LC-tank ESD protection design for 60-GHz RF applications.
ECCTD
Chun-Yu Lin, Li-Wei Chu, Shiang-Yu Tsai, Ming-Dou Ker, Tse-Hua Lu, Tsun-Lai Hsu, Ping-Fang Hung, Ming-Hsiang Song, Jeng-Chou Tseng, Tzu-Heng Chang, Ming-Hsien Tsai
2010 C conf
2×VDD-tolerant power-rail ESD clamp circuit with low standby leakage in 65-nm CMOS process.
ISCAS
Chun-Yu Lin, Ming-Dou Ker
2010 J jnl
Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection.
IEEE J. Solid State Circuits
Chih-Ting Yeh, Ming-Dou Ker
2010 J jnl
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wen-Yi Chen, Ming-Dou Ker
2010 J jnl
Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation.
Microelectron. Reliab.
Hui-Wen Tsai, Ming-Dou Ker
2010 J jnl
Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme.
Microelectron. Reliab.
Chun-Yu Lin, Ming-Dou Ker, Yuan-Wen Hsiao
2010 C conf
ESD protection circuit for high-voltage CMOS ICs with improved immunity against transient-induced latchup.
ISCAS
Ming-Dou Ker, Che-Lun Hsu, Wen-Yi Chen
2010 J jnl
Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-µm CMOS technology.
Microelectron. Reliab.
Shih-Hung Chen, Ming-Dou Ker
2010 J jnl
New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance.
IEEE Trans. Ind. Electron.
Ming-Dou Ker, Cheng-Cheng Yen
2009 J jnl
Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Hung Chen, Ming-Dou Ker
2009 — conf
Circuit solutions on ESD protection design for mixed-voltage I/O buffers in nanoscale CMOS.
CICC
Ming-Dou Ker, Chang-Tzu Wang
2009 — conf
Design of 2xVDD-tolerant I/O buffer with 1xVDD CMOS devices.
CICC
Ming-Dou Ker, Yan-Liang Lin
2009 J jnl
Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Tzu-Ming Wang, Ming-Dou Ker, Hung-Tai Liao
2009 J jnl
Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology.
IEEE J. Solid State Circuits
Chang-Tzu Wang, Ming-Dou Ker
2009 J jnl
Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits.
IEICE Trans. Electron.
Ming-Dou Ker, Yuan-Wen Hsiao
2009 C conf
Improvement on ESD Robustness of Lateral DMOS in High-voltage CMOS ICs by Body Current Injection.
ISCAS
Wen-Yi Chen, Ming-Dou Ker, Yeh-Ning Jou, Yeh-Jen Huang, Geeng-Lih Lin
2009 J jnl
Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process.
Microelectron. Reliab.
Yuan-Wen Hsiao, Ming-Dou Ker
2009 C conf
On the Design of Power-rail ESD Clamp Circuit with Consideration of Gate Leakage Current in 65-nm Low-voltage CMOS Process.
ISCAS
Ming-Dou Ker, Po-Yen Chiu, Fu-Yi Tsai, Yeong-Jar Chang
2008 C conf
2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue.
ISCAS
Ming-Dou Ker, Tzu-Ming Wang, Hung-Tai Liao
2008 — conf
An ESD-protected 5-GHz differential low-noise amplifier in a 130-nm CMOS process.
CICC
Yuan-Wen Hsiao, Ming-Dou Ker
2008 J jnl
Circuit Performance Degradation of Switched-Capacitor Circuit with Bootstrapped Technique due to Gate-Oxide Overstress in a 130-nm CMOS Process.
IEICE Trans. Electron.
Jung-Sheng Chen, Ming-Dou Ker
2008 — conf
Design of bandgap voltage reference circuit with all TFT devices on glass substrate in a 3-μm LTPS process.
CICC
Ting-Chou Lu, Ming-Dou Ker, Hsiao-Wen Zan, Chun-Hung Kuo, Chun-Huai Li, Yao-Jen Hsieh, Chun-Ting Liu
2008 — conf
Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process.
ICECS
Ming-Dou Ker, Tzu-Ming Wang, Fang-Ling Hu
2008 C conf
ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR.
ISCAS
Ming-Dou Ker, Chun-Yu Lin, Guo-Xuan Meng
2008 J jnl
Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test.
IEEE J. Solid State Circuits
Ming-Dou Ker, Cheng-Cheng Yen
2008 J jnl
Low-Capacitance and Fast Turn-on SCR for RF ESD Protection.
IEICE Trans. Electron.
Chun-Yu Lin, Ming-Dou Ker, Guo-Xuan Meng
2008 — conf
Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration.
APCCAS
Wen-Yi Chen, Ming-Dou Ker, Yeh-Jen Huang, Yeh-Ning Jou, Geeng-Lih Lin
2008 — conf
On-glass digital-to-analog converter with gamma correction for panel data driver.
ICECS
Tzu-Ming Wang, Yu-Hsuan Li, Ming-Dou Ker
2008 — conf
Optimization on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology.
ICECS
Shih-Hung Chen, Ming-Dou Ker
2007 — conf
A New Architecture for Charge Pump Circuit Without Suffering Gate-Oxide Reliability in Low-Voltage CMOS Processes.
ICECS
Tzu-Ming Wang, Wan-Yi Shen, Ming-Dou Ker
2007 J jnl
Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits.
Microelectron. Reliab.
Shih-Hung Chen, Ming-Dou Ker
2007 J jnl
An Output Buffer for 3.3-V Applications in a 0.13- μħbox m 1/2.5-V CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Lun Chen, Ming-Dou Ker
2007 — conf
CMOS Power Amplifier with ESD Protection Design Merged in Matching Network.
ICECS
Yu-Da Shiu, Bo-Shih Huang, Ming-Dou Ker
2007 — conf
Design of 2�?VDD-Tolerant I/O Buffer with Considerations of Gate-Oxide Reliability and Hot-Carrier Degradation.
ICECS
Hui-Wen Tsai, Ming-Dou Ker
2007 C conf
Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS Technology.
ISCAS
Ming-Dou Ker, Hung-Tai Liao
2007 — conf
ESD protection design for Giga-Hz high-speed I/O interfaces in a 130-nm CMOS process.
SoCC
Yuan-Wen Hsiao, Ming-Dou Ker, Po-Yen Chiu, Chun Huang, Yuh-Kuang Tseng
2007 J jnl
Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology.
IEEE J. Solid State Circuits
Ming-Dou Ker, Shih-Hung Chen
2007 J jnl
Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology.
Microelectron. Reliab.
Ming-Dou Ker, Wei-Jen Chang
2007 J jnl
Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes.
IEEE Trans. Circuits Syst. II Express Briefs
Ming-Dou Ker, Shih-Lun Chen
2006 J jnl
Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique.
IEEE J. Solid State Circuits
Ming-Dou Ker, Shih-Lun Chen
2006 J jnl
Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes.
IEEE J. Solid State Circuits
Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
2006 C conf
Design on LVDS receiver with new delay-selecting technique for UXGA flat panel display applications.
ISCAS
Ming-Dou Ker, Chien-Hua Wu
2006 J jnl
Design on Power-Rail ESD Clamp Circuit for 3.3-V I/O Interface by Using Only 1-V/2.5-V Low-Voltage Devices in a 130-nm CMOS Process.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Dou Ker, Wen-Yi Chen, Kuo-Chun Hsu
2006 C conf
Design on new tracking circuit of I/O buffer in 0.13µm cell library for mixed-voltage application.
ISCAS
Zi-Ping Chen, Che-Hao Chuang, Ming-Dou Ker
2006 — conf
Dummy-Gate Structure to Improve ESD Robustness in a Fully-Salicided 130-nm CMOS Technology without Using Extra Salicide-Blocking Mask.
ISQED
Hsin-Chyh Hsu, Ming-Dou Ker
2006 — conf
ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS.
ISSCC
Ming-Dou Ker, Wei-Jen Chang, Chang-Tzu Wang, Wen-Yi Chen
2006 J jnl
ESD robustness of thin-film devices with different layout structures in LTPS technology.
Microelectron. Reliab.
Chih-Kang Deng, Ming-Dou Ker
2006 J jnl
Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board.
Microelectron. Reliab.
Kun-Hsien Lin, Ming-Dou Ker
2006 J jnl
Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology.
Microelectron. Reliab.
Shih-Hung Chen, Ming-Dou Ker
2006 — conf
Low-Power Wordline Voltage Generator for Low-Voltage Flash Memory.
ICECS
Tzu-Ming Wang, Ming-Dou Ker, Steve Yeh, Ya-Chun Chang
2006 — conf
Method to Evaluate Cable Discharge Event (CDE) Reliability of Integrated Circuits in CMOS Technology.
ISQED
Tai-Xiang Lai, Ming-Dou Ker
2006 J jnl
New Curvature-Compensation Technique for CMOS Bandgap Reference With Sub-1-V Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Ming-Dou Ker, Jung-Sheng Chen
2006 C conf
New matching methodology of low-noise amplifier with ESD protection.
ISCAS
Bo-Shih Huang, Ming-Dou Ker
2006 — conf
On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS ICs.
CICC
Ming-Dou Ker, Cheng-Cheng Yen, Pi-Chia Shih
2006 J jnl
Overview and Design of Mixed-Voltage I/O Buffers With Low-Voltage Thin-Oxide CMOS Transistors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
2006 J jnl
Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: design concept and circuit implementations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Dou Ker, Kun-Hsien Lin
2006 J jnl
Self-Substrate-Triggered Technique to Enhance Turn-On Uniformity of Multi-Finger ESD Protection Devices.
IEEE J. Solid State Circuits
Ming-Dou Ker, Jia-Huei Chen
2006 — conf
System-Level ESD Protection Design with On-Chip Transient Detection Circuit.
ICECS
Cheng-Cheng Yen, Ming-Dou Ker, Pi-Chia Shih
2005 J jnl
A CMOS Bandgap Reference Circuit for Sub-1-V Operation without Using Extra Low-Threshold-Voltage Device.
IEICE Trans. Electron.
Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu
2005 J jnl
A new Schmitt trigger circuit in a 0.13-μm 1/2.5-V CMOS process to receive 3.3-V input signals.
IEEE Trans. Circuits Syst. II Express Briefs
Shih-Lun Chen, Ming-Dou Ker
2005 — conf
Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications.
ISCAS (2)
Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
2005 — conf
ESD protection design for I/O cells in sub-130-nm CMOS technology with embedded SCR structure.
ISCAS (2)
Kun-Hsien Lin, Ming-Dou Ker
2005 J jnl
ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kun-Hsien Lin
2005 J jnl
ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ming-Dou Ker, Hsin-Chyh Hsu
2005 J jnl
Investigation on seal-ring rules for IC product reliability in 0.25-mum CMOS technology.
Microelectron. Reliab.
Shih-Hung Chen, Ming-Dou Ker
2005 J jnl
MOS-Bounded Diodes for On-Chip ESD Protection in Deep Submicron CMOS Process.
IEICE Trans. Electron.
Ming-Dou Ker, Kun-Hsien Lin, Che-Hao Chuang
2005 — conf
New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation.
ISCAS (4)
Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu
2005 J jnl
The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kun-Hsien Lin
2004 — conf
A CMOS bandgap reference circuit for sub-1-V operation without using extra low-threshold-voltage device.
ISCAS (1)
Ming-Dou Ker, Jung-Sheng Chen, Ching-Yun Chu
2004 — conf
A new Schmitt trigger circuit in a 0.13 µm 1/2.5 V CMOS process to receive 3.3 V input signals.
ISCAS (2)
Shih-Lun Chen, Ming-Dou Ker
2004 — conf
A new charge pump circuit dealing with gate-oxide reliability issue in low-voltage processes.
ISCAS (1)
Ming-Dou Ker, Shih-Lun Chen, Chia-Sheng Tsai
2004 J jnl
Design on ESD protection scheme for IC with power-down-mode operation.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kun-Hsien Lin
2004 — conf
Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-µm CMOS technology.
ISCAS (2)
Che-Hao Chuang, Ming-Dou Ker
2004 J jnl
Design optimization of ESD protection and latchup prevention for a serial I/O IC.
Microelectron. Reliab.
Chih-Yao Huang, Wei-Fang Chen, Song-Yu Chuan, Fu-Chien Chiu, Jeng-Chou Tseng, I-Cheng Lin, Chuan-Jane Chao, Len-Yi Leu, Ming-Dou Ker
2004 — conf
Design to Avoid the Over-Gate-Driven Effect on ESD Protection Circuits in Deep-Submicron CMOS Processes.
ISQED
Ming-Dou Ker, Wen-Yi Chen
2004 — conf
ESD protection design for IC with power-down-mode operation.
ISCAS (2)
Ming-Dou Ker, Kun-Hsien Lin
2004 — conf
Low-Voltage-Triggered PNP Devices for ESD Protection Design in Mixed-Voltage I/O Interface with Over-VDD and Under-VSS Signal Levels.
ISQED
Ming-Dou Ker, Wei-Jen Chang, Wen-Yu Lo
2003 — conf
Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC.
ISQED
Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang
2003 J jnl
Analysis and Prevention on NC-ball induced ESD Damages in a 683-Pin BGA Packaged Chipset IC.
Microelectron. Reliab.
Wen-Yu Lo, Ming-Dou Ker
2003 J jnl
Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product.
Microelectron. Reliab.
I-Cheng Lin, Chih-Yao Huang, Chuan-Jane Chao, Ming-Dou Ker
2003 — conf
Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit.
ISCAS (5)
Ming-Dou Ker, Chia-Sheng Tsai
2003 — conf
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits.
ISQED
Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng
2003 — conf
Interference of ESD protection diodes on RF performance in Giga-Hz RF circuits.
ISCAS (1)
Ming-Dou Ker, Chien-Ming Lee
2003 J jnl
Latchup-free ESD protection design with complementary substrate-triggered SCR devices.
IEEE J. Solid State Circuits
Ming-Dou Ker, Kuo-Chun Hsu
2003 J jnl
Substrate-triggered ESD protection circuit without extra process modification.
IEEE J. Solid State Circuits
Ming-Dou Ker, Tung-Yang Chen
2002 — conf
ESD Protection Design for Mixed-Voltage I/O Circuit with Substrate-Triggered Technique in Sub-Quarter-Micron CMOS Process.
ISQED
Ming-Dou Ker, Chien-Hui Chuang, Kuo-Chun Hsu, Wen-Yu Lo
2002 — conf
ESD protection circuits with novel MOS-bounded diode structures.
ISCAS (5)
Ming-Dou Ker, Che-Hao Chuang
2002 J jnl
ESD protection design for CMOS RF integrated circuits using polysilicon diodes.
Microelectron. Reliab.
Ming-Dou Ker, Chyh-Yih Chang
2002 J jnl
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers.
IEEE J. Solid State Circuits
Ming-Dou Ker, Chien-Hui Chuang
2002 — conf
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits.
ISCAS (5)
Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang
2002 — conf
On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process.
ISCAS (5)
Ming-Dou Ker, Kuo-Chun Hsu
2001 — conf
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's.
ICECS
Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh
2001 — conf
Compact Layout Rule Extraction for Latchup Prevention in a 0.25-?m Shallow-Trench-Isolation Silicided Bulk CMOS Process.
ISQED
Ming-Dou Ker, Wen-Yu Lo, Tung-Yang Chen, Howard Tang, S.-S. Chen, Mu-Chun Wang
2001 — conf
Design on ESD Protection Circuit with Very Low and Constant Input Capacitance.
ISQED
Tung-Yang Chen, Ming-Dou Ker
2001 — conf
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes.
ISCAS (4)
Ming-Dou Ker, Tung-Yang Chen
2001 — conf
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique.
ISCAS (4)
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win
2001 — conf
ESD test methods on integrated circuits: an overview.
ICECS
Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang
2001 J jnl
Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard.
Microelectron. Reliab.
Ming-Dou Ker, Yu-Yu Sung
2001 — conf
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-μm salicided CMOS process.
ICECS
Ming-Dou Ker, Che-Hao Chuang, Wen-Yu Lo
2001 J jnl
On-chip ESD protection design by using polysilicon diodes in CMOS process.
IEEE J. Solid State Circuits
Ming-Dou Ker, Tung-Yang Chen, Tai-Ho Wang, Chung-Yu Wu
2000 C conf
Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications.
ISCAS
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang
2000 J jnl
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-μm silicide CMOS process.
IEEE J. Solid State Circuits
Ming-Dou Ker, Wen-Yu Lo
2000 J jnl
ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications.
IEEE J. Solid State Circuits
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu, Hun-Hsien Chang
2000 C conf
Mew diode string design with very low leakage current for using in power supply ESD clamp circuits.
ISCAS
Ming-Dou Ker, Wen-Yu Lo, Hun-Hsien Chang
1999 — conf
ESD buses for whole-chip ESD protection.
ISCAS (1)
Ming-Dou Ker, Hun-Hsien Chang, Tung-Yang Chen
1999 — conf
New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC's.
CICC
Ming-Dou Ker, Wen-Yu Lo, Chung-Yu Wu
1998 — conf
CMOS on-chip ESD protection design with substrate-triggering technique.
ICECS
Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Wu
1998 — conf
Electrostatic discharge protection circuits in CMOS IC's using the lateral SCR devices: an overview.
ICECS
Ming-Dou Ker
1998 — conf
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology.
CICC
Ming-Dou Ker, Jeng-Jie Peng
1998 — conf
Novel cascode NCLSCR/PCLSCR design with tunable holding voltage for safe whole-chip ESD protection.
CICC
Ming-Dou Ker, Hun-Hsien Chang
1997 J jnl
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS ICs.
IEEE J. Solid State Circuits
Ming-Dou Ker, Hun-Hsien Chang, Chung-Yu Wu
1997 J jnl
ESD protection for CMOS output buffer by using modified LVTSCR devices with high trigger current.
IEEE J. Solid State Circuits
Ming-Dou Ker
1996 J jnl
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.
IEEE Trans. Very Large Scale Integr. Syst.
Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang
1995 C conf
Complementary-LVTSCR ESD Protection Scheme for Submicron CMOS IC's.
ISCAS
Ming-Dou Ker, Chung-Yu Wu, Hun-Hsien Chang, Tao Cheng, Tain-Shun Wu
1992 J jnl
A new on-chip ESD protection circuit with dual parasitic SCR structures for CMOS VLSI.
IEEE J. Solid State Circuits
Chung-Yu Wu, Ming-Dou Ker, Chung-Yuan Lee, Joe Ko