Mineo Kaneko

98 papers A 1C 29Misc 1Journal 23Unranked 44
YearRankTypeTitle / Venue / Authors
2024 C conf
Design Automation for Charge Recovery Logic.
ISCAS
Yilmaz Ege Gonul, Leo Filippini, Junghoon Oh, Ragh Kuttappa, Scott Lerner, Mineo Kaneko, Baris Taskin
2024 J jnl
Energy Balancing of Power System Considering Periodic Behavioral Pattern of Renewable Energy Sources and Demands.
IEEE Access
Saher Javaid, Mineo Kaneko, Yasuo Tan
2024 J jnl
ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yuya Ushioda, Mineo Kaneko
2024 — conf
Improved Worst-case Modeling for Energy Balancing Considering Periodic Behavioral Patterns.
ICCE-Taiwan
Saher Javaid, Mineo Kaneko, Yasuo Tan
2023 C conf
Macro Construction Rules and Optimization for Long Bit Parallel Prefix Adders.
ISCAS
Mineo Kaneko
2023 J jnl
Optimal Location and Sizing of Renewable Distributed Generators for Improving Robust Voltage Stability Against Uncontrollable Reactive Compensation.
IEEE Access
Akanit Kwangkaew, Siriya Skolthanarat, Chalie Charoenlarpnopparut, Mineo Kaneko
2023 — conf
Supply-Dominated Energy Balancing for Periodic Operation of Power System.
ICCE-Taiwan
Saher Javaid, Mineo Kaneko, Yasuo Tan
2022 C conf
Hardware Minimization of Two-Level Adiabatic Logic Based on Weighted Maximum Stable Set Problem.
ICCD
Yuya Ushioda, Mineo Kaneko
2022 — conf
LP-based Co-optimization of Power Generators and Power Storage Systems under the Condition of Safe Operation.
ICCE-TW
Saher Javaid, Mineo Kaneko, Yasuo Tan, Nouman Ashraf
2022 C conf
Three-Dimensional Flexible-Module Placement for Stacked Three-Dimensional Integration.
ISCAS
Tomohiro Noguchi, Omran Hindawi, Mineo Kaneko
2021 C conf
Minimum Structural Transformation in Parallel Prefix Adders and its Application to Search-Based Optimization.
ISCAS
Mineo Kaneko
2021 — conf
Storage Minimization Considering System Conditions of Power Flow System.
ICCE-TW
Saher Javaid, Mineo Kaneko, Yasuo Tan
2020 J jnl
High Level Congestion Detection from C/C++ Source Code for High Level Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masato Tatsuoka, Mineo Kaneko
2020 C conf
Insertion-Based Procedural Construction and Optimization of Parallel Prefix Adders.
ISCAS
Mineo Kaneko
2020 — conf
System Condition for Controllable Power Flow System Considering Reaction Delay.
ICCE-TW
Saher Javaid, Mineo Kaneko, Yasuo Tan
2020 — conf
Two-Graph Approach to Temperature Dependent Skew Scheduling.
ISQED
Mineo Kaneko
2019 — conf
A Linear Programming Model for Power Flow Control Problem Considering Controllable and Fluctuating Power Devices.
GCCE
Saher Javaid, Mineo Kaneko, Yasuo Tan
2019 C conf
A Novel Framework for Procedural Construction of Parallel Prefix Adders.
ISCAS
Mineo Kaneko
2019 — conf
Power Flow Management for Smart Grids: Considering Renewable Energy and Demand Uncertainty.
ICCE-TW
Saher Javaid, Mineo Kaneko, Yasuo Tan
2018 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Mineo Kaneko
2018 C conf
Prefix Sequence: Optimization of Parallel Prefix Adders using Simulated Annealing.
ISCAS
Takayuki Moto, Mineo Kaneko
2018 — conf
Wire congestion aware high level synthesis flow with source code compiler.
ICICDT
Masato Tatsuoka, Mineo Kaneko
2017 — conf
A random access analog memory with master-slave structure for implementing hexadecimal logic.
SoCC
Renyuan Zhang, Mineo Kaneko
2017 J jnl
Foreword.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Mineo Kaneko
2017 C conf
KKT-condition inspired solution of DVFS with limited number of voltage levels.
ISCAS
Mineo Kaneko
2017 J jnl
Latency-Aware Selection of Check Variables for Soft-Error Tolerant Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Junghoon Oh, Mineo Kaneko
2017 — conf
Margin aware timing test and tuning algorithm for post-silicon skew tuning.
MWSCAS
Mineo Kaneko
2016 C conf
A 16-valued logic FPGA architecture employing analog memory circuit.
ISCAS
Renyuan Zhang, Mineo Kaneko
2016 J jnl
Area-Efficient Soft-Error Tolerant Datapath Synthesis Based on Speculative Resource Sharing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Junghoon Oh, Mineo Kaneko
2016 — conf
KKT-condition based study on DVFS for heterogeneous task set.
APCCAS
Mineo Kaneko
2016 — conf
Mixed error correction scheme and its design optimization for soft-error tolerant datapaths.
APCCAS
Junghoon Oh, Mineo Kaneko
2016 — conf
Soft-Error Tolerant Datapath Synthesis Considering Adjacency Constraint between Components.
ISVLSI
Junghoon Oh, Mineo Kaneko
2015 — conf
A Novel Framework for Temperature Dependence Aware Clock Skew Scheduling.
ACM Great Lakes Symposium on VLSI
Mineo Kaneko
2015 C conf
A feasibility study of quaternary FPGA designs by implementing Neuron-MOS mechanism.
ISCAS
Renyuan Zhang, Mineo Kaneko
2015 C conf
Automated selection of check variables for area-efficient soft-error tolerant datapath synthesis.
ISCAS
Junghoon Oh, Mineo Kaneko
2015 — conf
Bitwidth-aware register allocation and binding for clock period minimization.
MWSCAS
Keisuke Inoue, Mineo Kaneko
2015 J jnl
Robust and Low-Power Digitally Programmable Delay Element Designs Employing Neuron-MOS Mechanism.
ACM Trans. Design Autom. Electr. Syst.
Renyuan Zhang, Mineo Kaneko
2014 — conf
A feasibility study on robust programmable delay element design based on neuron-MOS mechanism.
ACM Great Lakes Symposium on VLSI
Renyuan Zhang, Mineo Kaneko
2014 — conf
An ILP-Based Optimal Circuit Mapping Method for PLDs.
IPDPS Workshops
Hiroki Nishiyama, Masato Inagi, Shin'ichi Wakabayashi, Shinobu Nagayama, Keisuke Inoue, Mineo Kaneko
2014 C conf
Constrained binding and scheduling of triplicated algorithm for fault tolerant datapath synthesis.
ISCAS
Mineo Kaneko, Yutaka Tsuboishi
2014 — conf
Priority based maximum consuming power control in smart homes.
ISGT
Saher Umer, Mineo Kaneko, Yasuo Tan, Azman Osman Lim
2014 — conf
Scheduling of PDE setting and timing tests for post-silicon skew tuning with timing margin: [extended abstract].
ACM Great Lakes Symposium on VLSI
Mineo Kaneko
2013 J jnl
Dual-Edge-Triggered Flip-Flop-Based High-Level Synthesis with Programmable Duty Cycle.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keisuke Inoue, Mineo Kaneko
2013 J jnl
Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-Flops and Latches.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keisuke Inoue, Mineo Kaneko
2012 J jnl
A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keisuke Inoue, Mineo Kaneko
2012 — conf
An efficient approach for designing and minimizing reversible programmable logic arrays.
ACM Great Lakes Symposium on VLSI
Sajib Kumar Mitra, Lafifa Jamal, Mineo Kaneko, Hafiz Md. Hasan Babu
2012 — conf
Optimal register-type selection during resource binding in flip-flop/latch-based high-level synthesis.
ACM Great Lakes Symposium on VLSI
Keisuke Inoue, Mineo Kaneko
2012 — conf
Performance-driven register write inhibition in high-level synthesis under strict maximum-permissible clock latency range.
ASP-DAC
Keisuke Inoue, Mineo Kaneko
2012 C conf
Post-silicon skew tuning algorithm utilizing setup and hold timing tests.
ISCAS
Mineo Kaneko, Jian Li
2012 — conf
Register binding and domain assignment for multi-domain clock skew scheduling-aware high-level synthesis.
ISQED
Keisuke Inoue, Mineo Kaneko
2012 C conf
Reliable and low-power clock distribution using pre- and post-silicon delay adaptation in high-level synthesis.
ISCAS
Keisuke Inoue, Mineo Kaneko
2012 — conf
Statistical timing-yield driven scheduling and FU binding in latch-based datapath synthesis.
MWSCAS
Keisuke Inoue, Mineo Kaneko
2012 C conf
Timing-test scheduling for constraint-graph based post-silicon skew tuning.
ICCD
Mineo Kaneko
2011 — conf
A complete framework of simultaneous functional unit and register binding with skew scheduling.
ISQED
Mineo Kaneko
2011 J jnl
Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2011 C conf
Early planning for RT-level delay insertion during clock skew-aware register binding.
VLSI-SoC
Keisuke Inoue, Mineo Kaneko
2011 J jnl
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
2011 J jnl
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation.
Inf. Media Technol.
Keisuke Inoue, Mineo Kaneko
2011 J jnl
Framework for Latch-based High-level Synthesis Using Minimum-delay Compensation.
IPSJ Trans. Syst. LSI Des. Methodol.
Keisuke Inoue, Mineo Kaneko
2011 — conf
Ordered coloring-based resource binding for datapaths with improved skew-adjustability.
ACM Great Lakes Symposium on VLSI
Mineo Kaneko, Keisuke Inoue
2011 C conf
Variable-duty-cycle scheduling in double-edge-triggered flip-flop-based high-level synthesis.
ISCAS
Keisuke Inoue, Mineo Kaneko
2010 — conf
A Pseudo-Boolean Technique for Generating Compact Transition Tests with All-Output-Propagation Properties.
DELTA
Tsuyoshi Iwagaki, Mineo Kaneko
2010 — conf
A novel resource sharing model and high-level synthesis for delay variability-tolerant datapaths.
ACM Great Lakes Symposium on VLSI
Keisuke Inoue, Mineo Kaneko
2010 — conf
Optimal register assignment with minimum-delay compensation for latch-based design.
APCCAS
Keisuke Inoue, Mineo Kaneko
2009 — conf
On the derivation of a minimum test set in high quality transition testing.
LATW
Tsuyoshi Iwagaki, Mineo Kaneko
2009 J jnl
Optimal Register Assignment with Minimum-Path Delay Compensation for Variation-Aware Datapaths.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2009 — conf
Safe clocking for the setup and hold timing constraints in datapath synthesis.
ACM Great Lakes Symposium on VLSI
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2009 C conf
Solvability of Simultaneous Control Step and Timing Skew Assignments in High Level Synthesis.
ISCAS
Takayuki Obata, Mineo Kaneko
2008 C conf
Concurrent skew and control step assignments in RT-level datapath synthesis.
ISCAS
Takayuki Obata, Mineo Kaneko
2008 J jnl
Novel Register Sharing in Datapath for Structural Robustness against Delay Variation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008 C conf
Safe clocking register assignment in datapath synthesis.
ICCD
Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
2008 J jnl
Simultaneous Optimization of Skew and Control Step Assignments in RT-Datapath Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Takayuki Obata, Mineo Kaneko
2007 A conf
Efficient path delay test generation based on stuck-at test generation using checker circuitry.
ICCAD
Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara
2007 — conf
Extended register-sharing in the synthesis of dual-rail two-phase asynchronous datapath.
ACM Great Lakes Symposium on VLSI
Koji Ohashi, Mineo Kaneko
2007 J jnl
Statistical Analysis Driven Synthesis of Application Specific Asynchronous Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Koji Ohashi, Mineo Kaneko
2006 — conf
Minimal Set of Essential Resource Disjoint Pairs for Exploring Feasible 3D Schedules.
APCCAS
Mineo Kaneko
2005 C conf
Statistical Analysis Driven Synthesis of Asynchronous Systems.
ICCD
Koji Ohashi, Mineo Kaneko
2005 — conf
Statistical schedule length analysis in asynchronous datapath synthesis.
ISCAS (1)
Koji Ohashi, Mineo Kaneko
2003 — conf
Fault tolerant datapath based on algorithm redundancy and vote-writeback mechanism.
ISCAS (5)
Mineo Kaneko, Kazuaki Oshio
2002 — conf
3D scheduling based on code space exploration for dynamically reconfigurable systems.
ISCAS (5)
Mineo Kaneko, Jun'ichi Yokoyama, Satoshi Tayu
2002 J jnl
Assignment-Driven Loop Pipeline Scheduling and Its Application to Data-Path Synthesis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Toshiyuki Yorozuya, Koji Ohashi, Mineo Kaneko
2002 J jnl
Characterization and Computation of Steiner Routing Based on Elmore's Delay Model.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Satoshi Tayu, Mineo Kaneko
2002 — conf
Characterization and computation of Steiner wiring based on Elmore's delay model.
APCCAS (2)
Satoshi Tayu, Mineo Kaneko
2002 — conf
Heuristic assignment-driven scheduling for data-path synthesis.
ISCAS (4)
Koji Ohashi, Mineo Kaneko
2002 — conf
Two-dimensional placement method based on divide-and-replacement.
APCCAS (2)
Yasuhiro Takashima, Akira Kaneko, Shinji Sato, Mineo Kaneko
2001 — conf
Extended dimensional threshold filtering-a bridge between FIR filter and median type filter.
ISCAS (2)
Mineo Kaneko, Yasuaki Maekawa
2000 — conf
An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays.
ISPAN
Satoshi Tayu, Motoyasu Katsura, Mineo Kaneko
2000 C conf
An efficient scheme based on EMPDC graph model in synthesizing fault tolerant FIR filter.
ISCAS
Choon-Sik Park, Mineo Kaneko
2000 C conf
Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis.
ICCD
Koji Ohashi, Mineo Kaneko, Satoshi Tayu
2000 C conf
Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications.
ISCAS
Mineo Kaneko, Yoshitaka Nishio, Satoshi Tayu
1999 — conf
Analysis and suppression of unnecessary transitions in weakly complementary MOS logic networks for low power.
ISCAS (1)
Mineo Kaneko
1998 J jnl
VLSI/PCB placement with obstacles based on sequence pair.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
1997 Misc conf
Adaptive AR spectral estimation based on multi-band decomposition of the linear prediction error with variable forgetting factors.
ICASSP
Fernando Gil Vianna Resende Jr., Paulo S. R. Diniz, Mineo Kaneko, Akinori Nishihara
1997 — conf
VLSI/PCB placement with obstacles based on sequence-pair.
ISPD
Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko
1994 C conf
A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach.
ISCAS
Sarwono Sutikno, Mineo Kaneko, Mahoki Onoda
1994 C conf
AR Spectrum Estimation Based on Wavelet Representation.
ISCAS
Fernando Gil Resende, Keiichi Tokuda, Mineo Kaneko
1994 C conf
Oscillation Fault Diagnosis for Analog Circuits based on Boundary Search with Perturbation Model.
ISCAS
Mineo Kaneko, Kazuhiro Sakaguchi
1993 C conf
A Novel Capacitor Placement Strategy in ASCCOT: Automatic Layouter for Switched Capacitor Circuits.
ISCAS
Mineo Kaneko, Masahiro Masuda, Tomohiro Hayashi