Mincent Lee - RankMe

17 papers A* 1A 4Misc 2Journal 5Unranked 5

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao
2020	—	`conf`	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2020	A	`conf`	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2020	—	`conf`	Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. ITC-Asia Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2019	A	`conf`	High Quality Test Methodology for Highly Reliable Devices. ITC Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang
2017	J	`jnl`	A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2017	J	`jnl`	Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	J	`jnl`	A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	J	`jnl`	Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	A*	`conf`	Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2014	—	`conf`	A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen
2014	A	`conf`	Redundancy architectures for channel-based 3D DRAM yield improvement. ITC Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2013	—	`conf`	Exploration Methodology for 3D Memory Redundancy Architectures under Redundancy Constraints. Asian Test Symposium Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
2012	Misc	`conf`	A Memory Failure Pattern Analyzer for memory diagnosis and repair. VTS Bing-Yang Lin, Mincent Lee, Cheng-Wen Wu
2012	A	`conf`	A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang
2012	Misc	`conf`	Cost modeling and analysis for interposer-based three-dimensional IC. VTS Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu
2011	J	`jnl`	A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mincent Lee, Li-Ming Denq, Cheng-Wen Wu