Min Zhao

27 papers A* 6A 7C 1Journal 7Unranked 6
YearRankTypeTitle / Venue / Authors
2010 J jnl
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
2008 — conf
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding.
ISQED
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jiang Hu
2008 J jnl
Power Grid Analysis and Optimization Using Algebraic Multigrid.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
2007 A conf
A novel technique for incremental analysis of on-chip power distribution networks.
ICCAD
Yuhong Fu, Rajendran Panda, Ben Reschke, Savithri Sundareswaran, Min Zhao
2007 A conf
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding.
ICCAD
Xiaoji Ye, Peng Li, Min Zhao, Rajendran Panda, Jiang Hu
2007 A* conf
On-Chip Decoupling Capacitance and P/G Wire Co-optimization for Dynamic Noise.
DAC
Min Zhao, Rajendran Panda, Ben Reschke, Yuhong Fu, Trudi Mewett, Sri Chandrasekaran, Savithri Sundareswaran, Shu Yan
2006 A* conf
A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming.
DAC
Min Zhao, Rajendran Panda, Savithri Sundareswaran, Shu Yan, Yuhong Fu
2006 A conf
Fast decap allocation based on algebraic multigrid.
ICCAD
Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen
2006 J jnl
Optimal placement of power-supply pads and pins.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2005 — conf
Timing driven track routing considering coupling capacitance.
ASP-DAC
Di Wu, Jiang Hu, Min Zhao, Rabi N. Mahapatra
2004 A conf
Exploiting level sensitive latches in wire pipelining.
ICCAD
V. Seth, Min Zhao, Jiang Hu
2004 — conf
Layer assignment for crosstalk risk minimization.
ASP-DAC
Di Wu, Jiang Hu, Rabi N. Mahapatra, Min Zhao
2004 A* conf
Optimal placement of power supply pads and pins.
DAC
Min Zhao, Yuhong Fu, Vladimir Zolotov, Savithri Sundareswaran, Rajendran Panda
2003 J jnl
Fast on-chip inductance simulation using a precorrected-FFT method.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2003 — conf
Statistical delay computation considering spatial correlations.
ASP-DAC
Aseem Agarwal, David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran, Min Zhao, Kaushik Gala, Rajendran Panda
2003 — conf
Table look-up based compact modeling for on-chip interconnect timing and noise analysis.
ISCAS (4)
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2002 A conf
A precorrected-FFT method for simulating on-chip inductance.
ICCAD
Haitian Hu, David T. Blaauw, Vladimir Zolotov, Kaushik Gala, Min Zhao, Rajendran Panda, Sachin S. Sapatnekar
2002 J jnl
Hierarchical analysis of power distribution networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, David T. Blaauw
2002 J jnl
Technology mapping algorithms for domino logic.
ACM Trans. Design Autom. Electr. Syst.
Min Zhao, Sachin S. Sapatnekar
2002 — conf
Worst case clock skew under power supply variations.
Timing Issues in the Specification and Synthesis of Digital Systems
Min Zhao, Kaushik Gala, Vladimir Zolotov, Yuhong Fu, Rajendran Panda, R. Ramkumar, Bhuwan K. Agrawal
2001 A* conf
A New Structural Pattern Matching Algorithm for Technology Mapping.
DAC
Min Zhao, Sachin S. Sapatnekar
2001 A* conf
Inductance 101: Analysis and Design Issues.
DAC
Kaushik Gala, David T. Blaauw, Junfeng Wang, Vladimir Zolotov, Min Zhao
2000 C conf
Dual-monotonic domino gate mapping and optimal output phase assignment of domino logic.
ISCAS
Min Zhao, Sachin S. Sapatnekar
2000 A* conf
Hierarchical analysis of power distribution networks.
DAC
Min Zhao, Rajendran Panda, Sachin S. Sapatnekar, Tim Edwards, Rajat Chaudhry, David T. Blaauw
2000 J jnl
Timing-driven partitioning and timing optimization of mixedstatic-domino implementations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Min Zhao, Sachin S. Sapatnekar
1999 A conf
Timing-driven partitioning for two-phase domino and mixed static/domino implementations.
ICCAD
Min Zhao, Sachin S. Sapatnekar
1998 A conf
Technology mapping for domino logic.
ICCAD
Min Zhao, Sachin S. Sapatnekar