Min Chen

11 papers A* 2A 2Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2014 J jnl
Recovery modeling of negative bias temperature instability (NBTI) for SPICE-compatible circuit aging simulators.
ACM J. Emerg. Technol. Comput. Syst.
Haldun Küflüoglu, Cathy Chancellor, Min Chen, Claude Cirba, Vijay Reddy
2014 J jnl
Reliability improvement of logic and clock paths in power-efficient designs.
ACM J. Emerg. Technol. Comput. Syst.
Senthil Arasu, Mehrdad Nourani, Vijay Reddy, John M. Carulli Jr., Gautam Kapila, Min Chen
2013 — conf
ACE: A robust variability and aging sensor for high-k/metal gate SoC.
ESSDERC
Min Chen, Vijay Reddy, Srikanth Krishnan, Jay Ondrusek, Yu Cao
2012 J jnl
Asymmetric Aging and Workload Sensitive Bias Temperature Instability Sensors.
IEEE Des. Test Comput.
Min Chen, Vijay Reddy, Srikanth Krishnan, Venkatesh Srinivasan, Yu Cao
2011 J jnl
Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness.
IEEE Trans. Very Large Scale Integr. Syst.
Yun Ye, Frank Liu, Min Chen, Sani R. Nassif, Yu Cao
2010 A* conf
In-situ characterization and extraction of SRAM variability.
DAC
Srivatsan Chellappa, Jia Ni, Xiaoyin Yao, Nathan D. Hindman, Jyothi Velamala, Min Chen, Yu Cao, Lawrence T. Clark
2009 J jnl
Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation.
IEEE Trans. Very Large Scale Integr. Syst.
Min Chen, Wei Zhao, Frank Liu, Yu Cao
2009 A conf
Modeling of layout-dependent stress effect in CMOS design.
ICCAD
Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao
2009 A* conf
Variability analysis under layout pattern-dependent rapid-thermal annealing process.
DAC
Yun Ye, Frank Liu, Min Chen, Yu Cao
2007 A conf
Fast statistical circuit analysis with finite-point based transistor model.
DATE
Min Chen, Wei Zhao, Frank Liu, Yu Cao
2006 — conf
Analysis of Pulse Signaling for Low-Power On-Chip Global Bus Design.
ISQED
Min Chen, Yu Cao