Min-Seong Choo

29 papers C 1Journal 14Unranked 14

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Pattern-Dependent Pulse Filtering Technique for Low-Jitter Injection-Locked CDR in 28-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. Junhak Kim, Young-Wook Kim, Sinho Lee, Yoojin Jung, Min-Seong Choo, Kwanseo Park
2025	J	`jnl`	A 14-to-32-Gb/s Deadzone-Free Referenceless CDR With Autocovariance-Based Seamless Frequency Detector in 40-nm CMOS Technology. IEEE J. Solid State Circuits Hong-Seok Choi, Jae-Geon Lee, Seung-Hwan Gong, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Kwanseo Park, Min-Seong Choo
2025	J	`jnl`	A Supply Noise-Insensitive Ring DCO With a Self-Biased Shunt Regulator Array in Wide-Range Digital PLL. IEEE Trans. Very Large Scale Integr. Syst. Kyungmin Baek, Jiho Kim, Kahyun Kim, Deog-Kyoon Jeong, Min-Seong Choo
2025	—	`conf`	An Implementation of a DSP-Based PAM-4 Digital Equalizer with 32-Way TI-ADC. ICEIC Sang-Hyeon Ok, Dong-Hoe Heo, Jae-Geon Lee, Seung-Mo Jin, Kwang-Ho Lee, Daniel Jeong, Min-Seong Choo
2024	J	`jnl`	3.2-GHz Digital Phase-Locked Loop With Autocorrelation-Based Direct Jitter Correction. IEEE Trans. Circuits Syst. II Express Briefs Gijin Park, Sun-Ho Yeom, InWoo Jang, Dongjun Lee, Jaeduk Han, Min-Seong Choo
2024	—	`conf`	A 14-to-32-Gb/s Deadzone-Free Referenceless CDR with Autocovariance-based Frequency Detector in 40-nm CMOS Technology. A-SSCC Hong-Seok Choi, Jae-Geon Lee, Kwang-Ho Lee, Daehyun Koh, Jung-Woo Sull, Hyungrok Do, Chan-Ho Kye, Deog-Kyoon Jeong, Min-Seong Choo
2024	—	`conf`	A 2T1C eDRAM-based Compute-In-Memory Macro with 8-to-l Column Multiplexing Scheme for Highly Sparse Binarized Deep Neural Networks. ISOCC Shin-Uk Kang, Seung-Mo Jin, Min-Gwon Song, Dong-hyun Lee, Woo-Suk Jung, Min-Seong Choo
2024	—	`conf`	An Analysis of 32-Gb/s and Full-Rate Phase Interpolator based Clock and Data Recovery. ICEIC Dong-Hoe Heo, Tae-Hyeon Kim, Kwang-Ho Lee, Min-Seong Choo
2024	—	`conf`	Analysis of ADC Quantization Effect in Processing-In-Memory Macro in Various Low-Precision Deep Neural Networks. ICEIC Seung-Mo Jin, Shin-Uk Kang, Min-Seong Choo
2024	J	`jnl`	Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Chan-Ho Kye, Yu-Jin Byeon, Kyojin Choo, Min-Seong Choo
2024	—	`conf`	Hardware and Software Co-Simulation Methodology for Processing-in-Memory Bitcell application. ICEIC Jae-Gun Lee, Shin-Uk Kang, Min-Seong Choo
2024	J	`jnl`	High-Precision Built-In Phase Noise Measurement Circuit With a Hybrid ΔΣ Time-to-Digital Converter for SoC Clocking Applications. IEEE Trans. Circuits Syst. II Express Briefs Jihun Choi, Sangwook Na, Hojin Kim, Hyungdong Roh, Youngjae Cho, Michael Choi, Min-Seong Choo, Jeongjin Roh
2023	J	`jnl`	An Automated Design Methodology for Ring Voltage-Controlled Oscillators in Nanometer CMOS Technologies. IEEE Access Dongjun Lee, Gijin Park, Jaeduk Han, Min-Seong Choo
2023	—	`conf`	Direct Phase Control in Digital Phase-Locked Loop Mitigating Loop Delay Effect inside Digital Filter. ICEIC InWoo Jang, Min-Seong Choo
2023	—	`conf`	Radiation-Hardened Processing-In-Memory Crossbar Array With Hybrid Synapse Devices for Space Application. ICEIC Shin-Uk Kang, Jin-Woo Han, Min-Seong Choo
2022	—	`conf`	A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. ESSCIRC Yeonggeun Song, Kyoungjoon Ha, Han-Gon Ko, Min-Seong Choo, Deog-Kyoon Jeong
2021	J	`jnl`	A 4-20-Gb/s 1.87-pJ/b Continuous-Rate Digital CDR Circuit With Unlimited Frequency Acquisition Capability in 65-nm CMOS. IEEE J. Solid State Circuits Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2021	J	`jnl`	A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong
2019	J	`jnl`	A 10-Gb/s, 0.03-mm IEEE J. Solid State Circuits Min-Seong Choo, Kwanseo Park, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2019	J	`jnl`	A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. IEEE Trans. Circuits Syst. II Express Briefs Min-Seong Choo, Yeonggeun Song, Sung-Yong Cho, Han-Gon Ko, Kwanseo Park, Deog-Kyoon Jeong
2019	—	`conf`	A 4-to-20Gb/s 1.87pJ/b Referenceless Digital CDR With Unlimited Frequency Detection Capability in 65nm CMOS. VLSI Circuits Kwanseo Park, Kwangho Lee, Sung-Yong Cho, Jinhyung Lee, Jeongho Hwang, Min-Seong Choo, Deog-Kyoon Jeong
2019	—	`conf`	A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm ISSCC Minho Choi, Chan-Ho Kye, Jonghyun Oh, Min-Seong Choo, Deog-Kyoon Jeong
2018	—	`conf`	A 10-Gb/s, 0.03-mm A-SSCC Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2018	J	`jnl`	A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong
2018	J	`jnl`	An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. IEEE Trans. Circuits Syst. II Express Briefs Min-Seong Choo, Han-Gon Ko, Sung-Yong Cho, Kwangho Lee, Deog-Kyoon Jeong
2017	—	`conf`	29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong
2017	J	`jnl`	A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong
2016	C	`conf`	A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong
2015	—	`conf`	A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong