Min-Jer Wang - RankMe

30 papers A* 1A 8Misc 2Journal 6Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack. ITC Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutyunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan
2020	—	`conf`	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC-Asia Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2020	A	`conf`	A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices. ITC Chien-Hui Chuang, Kuan-Wei Hou, Cheng-Wen Wu, Mincent Lee, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2020	—	`conf`	Novel Circuit Probing for Tiny Inductor. ITC-Asia Chia-Heng Tsai, Chi-Chang Lai, Hao Chen, Min-Jer Wang
2020	—	`conf`	Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill. ITC-Asia Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen, Min-Jer Wang
2019	A	`conf`	High Quality Test Methodology for Highly Reliable Devices. ITC Hao Chen, Mincent Lee, Liang-Yen Chen, Min-Jer Wang
2017	J	`jnl`	A Built-Off Self-Repair Scheme for Channel-Based 3D Memories. IEEE Trans. Computers Hsuan-Hung Liu, Bing-Yang Lin, Cheng-Wen Wu, Wan-Ting Chiang, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2017	—	`conf`	Fan-out wafer level chip scale package testing. ITC-Asia Hao Chen, Hung-Chih Lin, Min-Jer Wang
2017	J	`jnl`	Test Cost Reduction Methodology for InFO Wafer-Level Chip-Scale Package. IEEE Des. Test Kai-Li Wang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2017	—	`conf`	Testing-for-manufacturing (TFM) for ultra-thin IPD on InFO. ITC-Asia Tang-Jung Chiu, Yu-Lun Tseng, Yen-Cheng Lin, Yi-Chen Wang, Hung-Chih Lin, Min-Jer Wang
2016	J	`jnl`	A Local Parallel Search Approach for Memory Failure Pattern Identification. IEEE Trans. Computers Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	J	`jnl`	Configurable Cubical Redundancy Schemes for Channel-Based 3-D DRAM Yield Improvement. IEEE Des. Test Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2016	A*	`conf`	Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package. DAC Yu-Chieh Huang, Bing-Yang Lin, Cheng-Wen Wu, Mincent Lee, Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2015	—	`conf`	Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	—	`conf`	A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	J	`jnl`	A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application. IEEE J. Solid State Circuits Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta
2014	—	`conf`	A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	Misc	`conf`	A 4-GHz universal high-frequency on-chip testing platform for IP validation. VTS Ping-Lin Yang, Cheng-Chung Lin, Ming-Zhang Kuo, Sang-Hoo Dhong, Chien-Min Lin, Kevin Huang, Ching-Nen Peng, Min-Jer Wang
2014	—	`conf`	A novel DFT architecture for 3DIC test, diagnosis and repair. VLSI-DAT Mincent Lee, Saman Adham, Min-Jer Wang, Ching-Nen Peng, Hung-Chih Lin, Sen-Kuei Hsu, Hao Chen
2014	—	`conf`	Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS VLSI-DAT Sandeep Kumar Goel, Min-Jer Wang, Saman Adham, Ashok Mehta, Frank Lee
2014	J	`jnl`	On Improving Interconnect Defect Diagnosis Resolution and Yield for Interposer-Based 3-D ICs. IEEE Des. Test Chun-Chuan Chi, Bing-Yang Lin, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin, Ching-Nen Peng
2014	A	`conf`	Redundancy architectures for channel-based 3D DRAM yield improvement. ITC Bing-Yang Lin, Wan-Ting Chiang, Cheng-Wen Wu, Mincent Lee, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2014	A	`conf`	Wafer Level Chip Scale Package copper pillar probing. ITC Hao Chen, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2013	Misc	`conf`	3D-IC interconnect test, diagnosis, and repair. VTS Chun-Chuan Chi, Cheng-Wen Wu, Min-Jer Wang, Hung-Chih Lin
2013	—	`conf`	A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm CICC Ming-Zhang Kuo, Osamu Takahashi, Ping-Lin Yang, Cheng-Chung Lin, Min-Jer Wang, Ping-Wei Wang, Sang H. Dhong
2013	A	`conf`	Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. ITC Sandeep Kumar Goel, Saman Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, Frank Lee, Vivek Chickermane, Brion L. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Hyungdong Lee, Jungi Choi, Sangdoo Kim
2013	A	`conf`	Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch. ITC Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, Ching-Nen Peng, Min-Jer Wang
2012	—	`conf`	A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. VLSIC Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee
2012	A	`conf`	A memory yield improvement scheme combining built-in self-repair and error correction codes. ITC Tze-Hsin Wu, Po-Yuan Chen, Mincent Lee, Bin-Yen Lin, Cheng-Wen Wu, Chen-Hung Tien, Hung-Chih Lin, Hao Chen, Ching-Nen Peng, Min-Jer Wang
2008	—	`conf`	A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS. ISSCC Sergey Romanovsky, Atul Katoch, Arun Achyuthan, C. O'Connell, Sreedhar Natarajan, C. Huang, Chuan-Yu Wu, Min-Jer Wang, C. J. Wang, P. Chen, R. Hsieh