Min-Han Hsieh

12 papers C 8Journal 2Unranked 2
YearRankTypeTitle / Venue / Authors
2016 J jnl
A 6.7 MHz to 1.24 GHz 0.0318 mm
IEEE J. Solid State Circuits
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
2015 C conf
A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique.
ISCAS
Shuo-Hong Hung, Wei-Hao Kao, Kuan-I Wu, Yi-Wei Huang, Min-Han Hsieh, Charlie Chung-Ping Chen
2015 C conf
A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme.
ISCAS
Ai Chien, Shuo-Hong Hung, Kuan-I Wu, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
2013 C conf
A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS.
ISCAS
Wei-Sheng Cheng, Min-Han Hsieh, Shuo-Hong Hung, Szu-Yao Hung, Charlie Chung-Ping Chen
2013 C conf
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology.
ISCAS
Pang-Kai Liu, Szu-Yao Hung, Chang-Yi Liu, Min-Han Hsieh, Charlie Chung-Ping Chen
2013 C conf
System-impact analysis of a large-scale offshore wind farm connected to Taiwan power system.
IAS
Li Wang, Chun-Jui Yeh, Min-Han Hsieh, Cheng-Tai Wu, Chieh-Lung Lu
2012 C conf
A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm.
ISCAS
Min-Han Hsieh, Bing-Feng Lin, Yu-Shun Wang, Hao-Huei Chang, Charlie Chung-Ping Chen
2012 — conf
A 6.7MHz-to-1.24GHz 0.0318mm
ISSCC
Min-Han Hsieh, Liang-Hsin Chen, Shen-Iuan Liu, Charlie Chung-Ping Chen
2012 J jnl
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen
2011 C conf
A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique.
ISCAS
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Yi-Chi Wu, Bing-Feng Lin, Hsien-Chen Chiu, Charlie Chung-Ping Chen
2011 C conf
A 12 Gb/s chip-to-chip AC coupled transceiver.
ISCAS
Yu-Shun Wang, Min-Han Hsieh, Yi-Chi Wu, Chia-Ming Liu, Hsien-Chen Chiu, Bing-Feng Lin, Charlie Chung-Ping Chen
2011 — conf
An at-speed self-testable technique for the high speed domino adder.
CICC
Yu-Shun Wang, Min-Han Hsieh, Chia-Ming Liu, Chi-Wei Liu, James Chien-Mo Li, Charlie Chung-Ping Chen