| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2016 | J | jnl |
IEEE J. Solid State Circuits
|
| 2015 | C | conf |
ISCAS
|
| 2015 | C | conf |
ISCAS
|
| 2013 | C | conf |
ISCAS
|
| 2013 | C | conf |
ISCAS
|
| 2013 | C | conf |
IAS
|
| 2012 | C | conf |
ISCAS
|
| 2012 | — | conf |
ISSCC
|
| 2012 | J | jnl |
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2011 | C | conf |
ISCAS
|
| 2011 | C | conf |
ISCAS
|
| 2011 | — | conf |
CICC
|