Mikhail Asiatici

14 papers A* 1A 3B 2Journal 5Unranked 2
YearRankTypeTitle / Venue / Authors
2022 J jnl
Request, Coalesce, Serve, and Forget: Miss-Optimized Memory Systems for Bandwidth-Bound Cache-Unfriendly Applications on FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Mikhail Asiatici, Paolo Ienne
2021 J jnl
How Many CPU Cores is an FPGA Worth? Lessons Learned from Accelerating String Sorting on a CPU-FPGA System.
J. Signal Process. Syst.
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
2021 A* conf
Large-Scale Graph Processing on FPGAs with Caches for Thousands of Simultaneous Misses.
ISCA
Mikhail Asiatici, Paolo Ienne
2021 — —
Miss-Optimized Memory Systems: Turning Thousands of Outstanding Misses into Reuse Opportunities.
Mikhail Asiatici
2020 — conf
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort.
ASAP
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
2019 B conf
DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses.
FPL
Mikhail Asiatici, Paolo Ienne
2019 — conf
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA.
FPT
Gabor Csordas, Mikhail Asiatici, Paolo Ienne
2019 J jnl
Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips.
IEEE Access
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Paolo Ienne
2019 A conf
Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of Outstanding Misses in FPGAs.
FPGA
Mikhail Asiatici, Paolo Ienne
2018 A conf
FPGAs in the Datacenters: the Case of Parallel Hybrid Super Scalar String Sample Sort (pHS
FPGA
Mikhail Asiatici, Damian Maiorano, Paolo Ienne
2018 A conf
LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only).
FPGA
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne
2018 J jnl
Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires.
IEEE Access
Miku J. Laakso, Simon J. Bleiker, Jessica Liljeholm, Gustaf E. Martensson, Mikhail Asiatici, Andreas C. Fischer, Göran Stemme, Thorbjorn Ebefors, Frank Niklaus
2017 J jnl
Virtualized Execution Runtime for FPGA Accelerators in the Cloud.
IEEE Access
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne
2016 B conf
Designing a virtual runtime for FPGA accelerators in the cloud.
FPL
Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne