Mike Tien-Chien Lee

21 papers A* 4A 3Misc 1Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
1998 J jnl
ATM switch design by high-level modeling, formal verification and high-level synthesis.
ACM Trans. Design Autom. Electr. Syst.
Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee
1998 J jnl
Cost-free scan: a low-overhead scan path design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Chang Lin, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee, Kuang-Chien Chen
1998 J jnl
Eliminating false loops caused by sharing in control path.
ACM Trans. Design Autom. Electr. Syst.
Alan Su, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee
1998 A conf
Functional Scan Chain Testing.
DATE
Douglas Chang, Kwang-Ting Cheng, Malgorzata Marek-Sadowska, Mike Tien-Chien Lee
1998 J jnl
Power Analysis of a 32-bit Embedded Microcontroller.
VLSI Design
Vivek Tiwari, Mike Tien-Chien Lee
1998 J jnl
Test-point insertion: scan paths through functional logic.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
1997 A* conf
A Test Synthesis Approach to Reducing BALLAST DFT Overhead.
DAC
Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng
1997 J jnl
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Prototyping.
Des. Autom. Embed. Syst.
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
1997 — conf
On the control-subroutine implementation of subprogram synthesis.
ASP-DAC
Cheng-Tsung Hwang, Hsiao-Chien Weng, Yu-Chin Hsu, Mike Tien-Chien Lee
1997 J jnl
Power analysis and minimization techniques for embedded DSP software.
IEEE Trans. Very Large Scale Integr. Syst.
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
1996 A conf
A novel methodology for transistor-level power estimation.
ISLPED
Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Mike Tien-Chien Lee
1996 A* conf
Domain-Specific High-Level Modeling and Synthesis for ATM Switch Design Using VHDL.
DAC
Mike Tien-Chien Lee, Yu-Chin Hsu, Ben Chen, Masahiro Fujita
1996 — conf
Eliminating False Loops Caused by Sharing in Control Path.
ISSS
Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee
1996 Misc conf
Instruction Level Power Analysis and Optimization of Software.
VLSI Design
Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
1996 J jnl
Instruction level power analysis and optimization of software.
J. VLSI Signal Process.
Vivek Tiwari, Sharad Malik, Andrew Wolfe, Mike Tien-Chien Lee
1996 — conf
Sequential Permissible Functions and their Application to Circuit Optimization.
ED&TC
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kuang-Chien Chen, Mike Tien-Chien Lee
1996 A* conf
Test Point Insertion: Scan Paths through Combinational Logic.
DAC
Chih-Chang Lin, Malgorzata Marek-Sadowska, Kwang-Ting Cheng, Mike Tien-Chien Lee
1996 A* conf
Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures.
DAC
Guido Araujo, Sharad Malik, Mike Tien-Chien Lee
1995 A conf
Cost-free scan: a low-overhead scan path design methodology.
ICCAD
Chih-Chang Lin, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Kuang-Chien Chen
1995 — conf
Power analysis and low-power scheduling techniques for embedded DSP software.
ISSS
Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
1995 — conf
Power analysis of a 32-bit embedded microcontroller.
ASP-DAC
Vivek Tiwari, Mike Tien-Chien Lee