Mike Shuo-Wei Chen

92 papers A* 2A 4B 2Journal 34Unranked 50

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 0.052mm ISSCC Mostafa M. Ayesh, Mike Shuo-Wei Chen
2025	—	`conf`	11.2 A Blocker-Tolerant Receiver with VCO-Based Non-Uniform Multi-Level Time-Approximation Filter with -36dB EVM in 28nm CMOS. ISSCC Ce Yang, Shiyu Su, Mostafa M. Ayesh, Soumya Mahapatra, Maysara M. Hamada, Vinay Chenna, Hossein Hashemi, Mike Shuo-Wei Chen
2025	—	`conf`	26.1: A 24GHz Direct Digital Transmitter Using Multiphase Subharmonic Switching PA Achieving 3.2Gb/s Data Rate and -30.8dB EVM in 65nm CMOS. ISSCC Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo-Wei Chen
2025	J	`jnl`	A Blocker-Tolerant Receiver With VCO-Based Non-Uniform Multi-Level Time-Approximation Filter. IEEE J. Solid State Circuits Ce Yang, Shiyu Su, Mostafa M. Ayesh, Soumya Mahapatra, Maysara Hamada, Vinay Chenna, Hossein Hashemi, Mike Shuo-Wei Chen
2025	J	`jnl`	A Millimeter-Wave Direct Digital Transmitter Using Multiphase Subharmonic Switching PA. IEEE J. Solid State Circuits Soumya Mahapatra, Mostafa M. Ayesh, Ce Yang, Mayank Palaria, Shiyu Su, Aoyang Zhang, Mike Shuo-Wei Chen
2025	J	`jnl`	Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders. IEEE J. Solid State Circuits Shiyu Su, Qiaochu Zhang, Baishakhi Rani Biswas, Sandeep K. Gupta, Mike Shuo-Wei Chen
2024	—	`conf`	5.3 A 0.072mm ISSCC Mostafa M. Ayesh, Soumya Mahapatra, Ce Yang, Mike Shuo-Wei Chen
2024	—	`conf`	A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. VLSI Technology and Circuits Juzheng Liu, Ayman Shabra, Stacy Ho, Gabriele Manganaro, Mike Shuo-Wei Chen
2024	J	`jnl`	A Blocker-Tolerant Non-Uniform Sub-Sampling Receiver With a Non-Uniform Discrete-Time FIR Filter. IEEE J. Solid State Circuits Mostafa M. Ayesh, Soumya Mahapatra, Ce Yang, Mike Shuo-Wei Chen
2024	A	`conf`	A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. DATE Mutian Zhu, Mohsen Hassanpourghadi, Qiaochu Zhang, Mike Shuo-Wei Chen, Anthony F. J. Levi, Sandeep Gupta
2024	—	`conf`	A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. VLSI Technology and Circuits Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen
2024	J	`jnl`	Fractional-N Digital MDLL With Injection-Error Scrambling and Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
2024	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2023 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Mike Shuo-Wei Chen, Visvesh S. Sathe, Massimo Alioto, Jae-sun Seo, Hidehiro Shiga
2024	—	`conf`	Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm VLSI Technology and Circuits Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen
2023	—	`conf`	A 2GS/s 8.5-Bit Time-Based ADC using a Segmented Stochastic Flash TDC. CICC Shiyu Su, Qiaochu Zhang, Mike Shuo-Wei Chen
2023	—	`conf`	A Fractional-N Digital MDLL with Injection-Error Scrambling and Background Third-Order DTC Delay Equalizer Achieving -67dBc Fractional Spur. ISSCC Qiaochu Zhang, Hsiang-Chun Cheng, Shiyu Su, Mike Shuo-Wei Chen
2023	—	`conf`	A Memristor-Based Analog Accelerator for Solving Quadratic Programming Problems. CICC Hsiang-Chun Cheng, Shiyu Su, Mayank Palaria, Qiaochu Zhang, Ce Yang, Sushmit Hossain, Ryan M. Bena, Buyun Chen, Zerui Liu, Juzheng Liu, Rezwan A. Rasul, Quan Nguyen, Wei Wu, Mike Shuo-Wei Chen
2023	—	`conf`	Analog Kalman Filter with Integration and Digitization via a Shared Thyristor-Based VCO for Sensor Fusion in 65 nm CMOS. ESSCIRC Mayank Palaria, Shiyu Su, Hsiang-Chun Cheng, Rezwan A. Rasul, Qiaochu Zhang, Soumya Mahapatra, Chong-Fatt Law, Sushmit Hossain, Ryan M. Bena, Wei Wu, Quan Nguyen, Mike Shuo-Wei Chen
2023	J	`jnl`	Millimeter-Wave Receiver With Non-Uniform Time-Approximation Filter. IEEE J. Solid State Circuits Ce Yang, Shiyu Su, Mike Shuo-Wei Chen
2022	J	`jnl`	A 10-GS/s 8-bit 2850-μm IEEE J. Solid State Circuits Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
2022	—	`conf`	A 10GS/s 8b 25fJ/c-s 2850um ISSCC Juzheng Liu, Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
2022	J	`jnl`	A Fractional-N Digital MDLL With Background Two-Point DTC Calibration. IEEE J. Solid State Circuits Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2022	A*	`conf`	A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scrambling. DAC Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
2022	—	`conf`	Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. ASP-DAC Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
2022	—	`conf`	High-Speed Digital-to-Analog Converter Design Towards High Dynamic Range. CICC Shiyu Su, Mike Shuo-Wei Chen
2022	—	`conf`	Non-Uniform Sampling Data Converters: A Journey to Uncharted Circuits and Systems. VLSI-DAT Mike Shuo-Wei Chen
2022	J	`jnl`	SAW-Less Direct RF Transmitter With Multimode Noise Shaping and Tri-Level Time-Approximation Filter. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2022	—	`conf`	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. ASP-DAC Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	—	`conf`	26.6 A 5-to-6GHz Current-Mode Subharmonic Switching Digital Power Amplifier for Enhancing Power Back-Off Efficiency. ISSCC Aoyang Zhang, Ce Yang, Mostafa M. Ayesh, Mike Shuo-Wei Chen
2021	—	`conf`	29.4 A Fractional-N Digital MDLL with Background Two-Point DTC Calibration Achieving -60dBc Fractional Spur. ISSCC Qiaochu Zhang, Shiyu Su, Cheng-Ru Ho, Mike Shuo-Wei Chen
2021	—	`conf`	A 128x128 SRAM Macro with Embedded Matrix-Vector Multiplication Exploiting Passive Gain via MOS Capacitor for Machine Learning Application. CICC Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	—	`conf`	A 24-28 GHz Concurrent Harmonic and Subharmonic Tuning Class E/F2, 2/3 Subharmonic Switching Power Amplifier Achieving Peak/PBO Efficiency Enhancement. CICC Aoyang Zhang, Mostafa M. Ayesh, Soumya Mahapatra, Mike Shuo-Wei Chen
2021	J	`jnl`	A Module-Linking Graph Assisted Hybrid Optimization Framework for Custom Analog and Mixed-Signal Circuit Parameter Synthesis. ACM Trans. Design Autom. Electr. Syst. Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	J	`jnl`	A Time-Approximation Filter for Direct RF Transmitter. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2021	J	`jnl`	Analog/Mixed-Signal Circuit Synthesis Enabled by the Advancements of Circuit Architectures and Machine Learning Algorithms. CoRR Shiyu Su, Qiaochu Zhang, Mohsen Hassanpourghadi, Juzheng Liu, Rezwan A. Rasul, Mike Shuo-Wei Chen
2021	A*	`conf`	Circuit Connectivity Inspired Neural Network for Analog Mixed-Signal Functional Modeling. DAC Mohsen Hassanpourghadi, Shiyu Su, Rezwan A. Rasul, Juzheng Liu, Qiaochu Zhang, Mike Shuo-Wei Chen
2021	A	`conf`	From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. ICCAD Juzheng Liu, Shiyu Su, Meghna Madhusudan, Mohsen Hassanpourghadi, Samuel Saunders, Qiaochu Zhang, Rezwan A. Rasul, Yaguang Li, Jiang Hu, Arvind Kumar Sharma, Sachin S. Sapatnekar, Ramesh Harjani, Anthony Levi, Sandeep Gupta, Mike Shuo-Wei Chen
2021	—	`conf`	Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. ISSCC Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany
2021	J	`jnl`	TAFA: Design Automation of Analog Mixed-Signal FIR Filters Using Time Approximation Architecture. CoRR Shiyu Su, Qiaochu Zhang, Juzheng Liu, Mohsen Hassanpourghadi, Rezwan A. Rasul, Mike Shuo-Wei Chen
2020	—	`conf`	10.2 A SAW-Less Direct-Digital RF Modulator with Tri-Level Time-Approximation Filter and Reconfigurable Dual-Band Delta-Sigma Modulation. ISSCC Shiyu Su, Mike Shuo-Wei Chen
2020	—	`conf`	16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS. ISSCC Tzu-Fan Wu, Mike Shuo-Wei Chen
2020	J	`jnl`	A 12.8-Gbaud ADC-Based Wireline Receiver With Embedded IIR Equalizer. IEEE J. Solid State Circuits Jae-Won Nam, Mike Shuo-Wei Chen
2020	A	`conf`	CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. ICCAD Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen
2020	A	`conf`	Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. ICCAD Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen
2019	—	`conf`	A 1-5GHz Direct-Digital RF Modulator with an Embedded Time-Approximation Filter Achieving -43dB EVM at 1024 QAM. VLSI Circuits Shiyu Su, Mike Shuo-Wei Chen
2019	—	`conf`	A 12.8-Gbaud ADC-based NRZ/PAM4 Receiver with Embedded Tunable IIR Equalization Filter Achieving 2.43-pJ/b in 65nm CMOS. CICC Jae-Won Nam, Mike Shuo-Wei Chen
2019	—	`conf`	A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells. CICC Mohsen Hassanpourghadi, Mike Shuo-Wei Chen
2019	J	`jnl`	A Noise-Shaped VCO-Based Nonuniform Sampling ADC With Phase-Domain Level Crossing. IEEE J. Solid State Circuits Tzu-Fan Wu, Mike Shuo-Wei Chen
2019	J	`jnl`	A Subharmonic Switching Digital Power Amplifier for Power Back-Off Efficiency Enhancement. IEEE J. Solid State Circuits Aoyang Zhang, Mike Shuo-Wei Chen
2019	—	`conf`	A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier Achieving 31.4% Average Drain Efficiency. ISSCC Aoyang Zhang, Mike Shuo-Wei Chen
2019	J	`jnl`	A Watt-Level Phase-Interleaved Multi-Subharmonic Switching Digital Power Amplifier. IEEE J. Solid State Circuits Aoyang Zhang, Mike Shuo-Wei Chen
2018	J	`jnl`	A 12-Bit 1.6, 3.2, and 6.4 GS/s 4-b/Cycle Time-Interleaved SAR ADC With Dual Reference Shifting and Interpolation. IEEE J. Solid State Circuits Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
2018	J	`jnl`	A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <-67-dBc IM3 Within DC to 6-GHz Tunable Passbands. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2018	—	`conf`	A 16b 12GS/S single/dual-rate DAC with successive bandpass delta-sigma modulator achieving <-67dBc IM3 within DC-to-6GHz tunable passbands. ISSCC Shiyu Su, Mike Shuo-Wei Chen
2018	—	`conf`	A 200MHz-BW 0.13mm CICC Tzu-Fan Wu, Mike Shuo-Wei Chen
2018	—	`conf`	A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency. VLSI Circuits Aoyang Zhang, Mike Shuo-Wei Chen
2018	—	`conf`	A digital frequency synthesizer with dither-assisted pulling mitigation for simultaneous DCO and reference path coupling. ISSCC Cheng-Ru Ho, Mike Shuo-Wei Chen
2018	—	`conf`	A fractional-N digital PLL with background-dither-noise-cancellation loop achieving <-62.5dBc worst-case near-carrier fractional spurs in 65nm CMOS. ISSCC Cheng-Ru Ho, Mike Shuo-Wei Chen
2018	—	`conf`	Evolutions of SAR ADC: From high resolution to high speed regime. CICC Mike Shuo-Wei Chen
2017	J	`jnl`	A 6-b, 800-MS/s, 3.62-mW Nyquist Rate AC-Coupled VCO-Based ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Mohsen Hassanpourghadi, Praveen Kumar Sharma, Mike Shuo-Wei Chen
2017	J	`jnl`	A Flash-Based Non-Uniform Sampling ADC With Hybrid Quantization Enabling Digital Anti-Aliasing Filter. IEEE J. Solid State Circuits Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen
2017	—	`conf`	A time multiplexed network architecture for large-scale neuromorphic computing. MWSCAS Rezwan A. Rasul, Pedram Teimouri, Mike Shuo-Wei Chen
2016	—	`conf`	10.5 A digital PLL with feedforward multi-tone spur cancelation loop achieving <-73dBc fractional spur and <-110dBc Reference Spur in 65nm CMOS. ISSCC Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	—	`conf`	27.1 A 12b 2GS/s dual-rate hybrid DAC with pulsed timing-error pre-distortion and in-band noise Cancellation Achieving >74dBc SFDR up to 1GHz in 65nm CMOS. ISSCC Shiyu Su, Mike Shuo-Wei Chen
2016	J	`jnl`	A 12-Bit 2 GS/s Dual-Rate Hybrid DAC With Pulse-Error Pre-Distortion and In-Band Noise Cancellation Achieving > 74 dBc SFDR and <-80 dBc IM3 up to 1 GHz in 65 nm CMOS. IEEE J. Solid State Circuits Shiyu Su, Mike Shuo-Wei Chen
2016	—	`conf`	A 12-bit 1.6 GS/s interleaved SAR ADC with dual reference shifting and interpolation achieving 17.8 fJ/conv-step in 65nm CMOS. VLSI Circuits Jae-Won Nam, Mohsen Hassanpourghadi, Aoyang Zhang, Mike Shuo-Wei Chen
2016	J	`jnl`	A Digital PLL With Feedforward Multi-Tone Spur Cancellation Scheme Achieving <-73 dBc Fractional Spur and <-110 dBc Reference Spur in 65 nm CMOS. IEEE J. Solid State Circuits Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	J	`jnl`	A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. Cheng-Ru Ho, Mike Shuo-Wei Chen
2016	J	`jnl`	A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter. IEEE Trans. Circuits Syst. I Regul. Pap. Tzu-Fan Wu, Sourya Dey, Mike Shuo-Wei Chen
2016	J	`jnl`	An Embedded Passive Gain Technique for Asynchronous SAR ADC Achieving 10.2 ENOB 1.36-mW at 95-MS/s in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Jae-Won Nam, Mike Shuo-Wei Chen
2016	—	`conf`	Interference-induced DCO spur mitigation for digital phase locked loop in 65-nm CMOS. ESSCIRC Cheng-Ru Ho, Mike Shuo-Wei Chen
2015	J	`jnl`	A 12 bit 1 GS/s Dual-Rate Hybrid DAC With an 8 GS/s Unrolled Pipeline Delta-Sigma Modulator Achieving > 75 dB SFDR Over the Nyquist Band. IEEE J. Solid State Circuits Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
2015	—	`conf`	A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. CICC Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen
2014	—	`conf`	A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. VLSIC Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen
2014	J	`jnl`	Cross-Layer Modeling and Simulation of Circuit Reliability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu Cao, Jyothi Velamala, Ketul Sutaria, Mike Shuo-Wei Chen, Jonathan Ahlbin, Ivan Sanchez Esqueda, Michael Bajura, Michael Fritze
2013	—	`conf`	A 6b 800MS/s 3.62mW Nyquist AC-coupled VCO-based ADC in 65nm CMOS. CICC Praveen Kumar Sharma, Mike Shuo-Wei Chen
2013	—	`conf`	A 95-MS/s 11-bit 1.36-mW asynchronous SAR ADC with embedded passive gain in 65nm CMOS. CICC Jae-Won Nam, David Chiong, Mike Shuo-Wei Chen
2012	B	`conf`	A non-uniform sampling ADC architecture with embedded alias-free asynchronous filter. GLOBECOM Dylan Hand, Mike Shuo-Wei Chen
2012	—	`conf`	Overhead minimization techniques for digital phase-locked loop frequency synthesizer. MWSCAS Mike Shuo-Wei Chen
2011	—	`conf`	A 65nm dual-band 3-stream 802.11n MIMO WLAN SoC. ISSCC Shahram Abdollahi-Alibeik, David Weber, Hakan Dogan, William W. Si, Burcin Baytekin, Abbas Komijani, Richard Chang, Babak Vakili-Amini, MeeLan Lee, Haitao Gan, Yashar Rajavi, Hirad Samavati, Brian J. Kaczynski, Sang-Min Lee, Sotirios Limotyrakis, Hyunsik Park, Phoebe Chen, Paul Park, Mike Shuo-Wei Chen, Andrew Chang, Yangjin Oh, Jerry Jian-Ming Yang, Eric Chien-Chih Lin, Lalitkumar Nathawad, Keith Onodera, Manolis Terrovitis, Sunetra Mendis, Kai Shi, Srenik S. Mehta, Masoud Zargari, David K. Su
2010	J	`jnl`	A Calibration-Free 800 MHz Fractional-N Digital PLL With Embedded TDC. IEEE J. Solid State Circuits Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta
2010	—	`conf`	A calibration-free 800MHz fractional-N digital PLL with embedded TDC. ISSCC Mike Shuo-Wei Chen, David K. Su, Srenik S. Mehta
2009	J	`jnl`	Design and implementation of a CMO 802.11n SoC. IEEE Commun. Mag. Sundar G. Sankaran, Brian J. Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley
2008	—	`conf`	A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. ISSCC Lalitkumar Nathawad, Masoud Zargari, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Sunetra Mendis, Andrew Chang, Steve H. Jen, David K. Su, Bruce A. Wooley
2008	J	`jnl`	A Dual-Band CMOS MIMO Radio SoC for IEEE 802.11n Wireless LAN. IEEE J. Solid State Circuits Masoud Zargari, Lalitkumar Nathawad, Hirad Samavati, Srenik S. Mehta, Alireza Kheirkhahi, Phoebe Chen, Ke Gong, Babak Vakili-Amini, Justin A. Hwang, Mike Shuo-Wei Chen, Manolis Terrovitis, Brian J. Kaczynski, Sotirios Limotyrakis, Michael P. Mack, Haitao Gan, MeeLan Lee, Richard Chang, Hakan Dogan, Shahram Abdollahi-Alibeik, Burcin Baytekin, Keith Onodera, Suni Mendis, Andrew Chang, Yashar Rajavi, Steve Hung-Min Jen, David K. Su, Bruce A. Wooley
2007	—	`conf`	Impact of Sampling Jitter on Mostly-Digital Architectures for UWB Bio-Medical Applications. ICC Andrew Fort, Mike Shuo-Wei Chen, Robert W. Brodersen, Claude Desset, Piet Wambacq, Leo Van Biesen
2006	—	`conf`	A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS. ISSCC Mike Shuo-Wei Chen, Robert W. Brodersen
2006	B	`conf`	Digital Complex Signal Processing Techniques for Impulse Radio. GLOBECOM Mike Shuo-Wei Chen, Robert W. Brodersen
2006	J	`jnl`	Novel Radio Architectures for UWB, 60 GHz, and Cognitive Wireless Systems. EURASIP J. Wirel. Commun. Netw. Danijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Stanley Wang, Jing Yang, Robert W. Brodersen
2005	J	`jnl`	A Subsampling UWB Impulse Radio Architecture Utilizing Analytic Signaling. IEICE Trans. Electron. Mike Shuo-Wei Chen, Robert W. Brodersen
2005	—	`conf`	Future wireless systems: UWB, 60GHz, and cognitive radios. CICC Danijela Cabric, Mike Shuo-Wei Chen, David A. Sobel, Jing Yang, Robert W. Brodersen
2004	—	`conf`	A subsampling UWB radio architecture by analytic signaling. ICASSP (4) Mike Shuo-Wei Chen, Robert W. Brodersen