Mikaël Cassé

25 papers C 2Journal 3Unranked 20

Year	Rank	Type	Title / Venue / Authors
2025	C	`conf`	Cryogenic Circuit Performance Prediction Using Design-Oriented Model (SEKV) On 22nm FDSOI. ISCAS Brian Martinez, Hung-Chi Han, Flávio Enrico Bergamaschi, Quentin Schmidt, Antoine Faurie, Edoardo Charbon, Yvain Thonnart, Baptiste Jadot, Xavier Jehl, Mikaël Cassé, Christian C. Enz, Franck Badets
2025	—	`conf`	Self-Heating Effects in FDSOI Transistors at Cryogenic Temperature: A Spatial and Temporal Experimental Study (Invited). IRPS Mikaël Cassé, Flávio Enrico Bergamaschi, Quentin Berlingard
2024	—	`conf`	Experimental Decomposition of the Carrier Mobility in the Conduction Planes of 2-Level Stacked Nanowires. CCE Giovanni Almeida Matos, Jaime CalÇade Rodrigues, Michelly de Souza, Mikaël Cassé, Sylvain Barraud, Olivier Faynot, Marcelo Antonio Pavanello
2024	—	`conf`	LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. NewCAS Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Jose Lugo, Joao Azevedo, Sebastien Sadlo, Quentin Berlingard, Mikaël Cassé, Philippe Galy
2023	C	`conf`	Noise modeling using look-up tables and DC measurements for cryogenic applications. VLSI-SoC Giovani Britton, Salvador Mir, Estelle Lauga-Larroze, Benjamin Dormieu, Quentin Berlingard, Mikaël Cassé, Philippe Galy
2023	—	`conf`	RF performance of Standard, High-Resistivity and Trap-Rich Silicon substrates down to cryogenic temperature. ESSDERC Quentin Berlingard, M. Moulin, Jean-Philippe Michel, T. Fache, Ismael Charlet, C. Plantier, Z. Chalupa, Jose Lugo-Alvarez, Jean-Pierre Raskin, Louis Hutin, Mikaël Cassé
2023	—	`conf`	Transport characterization of CMOS-based devices fabricated with isotopically-enriched ESSDERC G. Elbaz, Mikaël Cassé, V. Labracherie, G. Roussely, Benoit Bertrand, Heimanu Niebojewski, Maud Vinet, F. Balestro, Matias Urdampilleta, Tristan Meunier, Bruna Cardoso Paz
2022	—	`conf`	Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K. IRPS Lauriane Contamin, Mikaël Cassé, Xavier Garros, Fred Gaillard, Maud Vinet, Philippe Galy, André Juge, Emmanuel Vincent, Silvano De Franceschi, Tristan Meunier
2022	—	`conf`	Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration. VLSI Technology and Circuits Tadeu Mota Frutuoso, Xavier Garros, Perrine Batude, Laurent Brunet, Joris Lacord, Benoit Sklénard, V. Lapras, Claire Fenouillet-Béranger, M. Ribotta, A. Magalhaes-Lucas, J. Kanyandekwe, R. Kies, G. Romano, Edoardo Catapano, Mikaël Cassé, Jose Lugo-Alvarez, Philippe Ferrari, Fred Gaillard
2022	—	`conf`	Specificities of linear Si QD arrays integration and characterization. VLSI Technology and Circuits Heimanu Niebojewski, Benoit Bertrand, Etienne Nowak, Thomas Bedecarrats, Bruna Cardoso Paz, Lauriane Contamin, Pierre-André Mortemousque, V. Labracherie, L. Brevard, H. Sahin, Jean Charbonnier, C. Thomas, Myriam Assous, Mikaël Cassé, Matias Urdampilleta, Yann-Michel Niquet, François Perruchot, Fred Gaillard, Silvano De Franceschi, Tristan Meunier, Maud Vinet
2021	—	`conf`	Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors. ESSDERC Michelly de Souza, Sylvain Barraud, Mikaël Cassé, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello
2021	—	`conf`	Impact of spacer interface charges on performance and reliability of low temperature transistors for 3D sequential integration. IRPS Tadeu Mota Frutuoso, Jose Lugo-Alvarez, Xavier Garros, Laurent Brunet, Joris Lacord, Louis Gerrer, Mikaël Cassé, Edoardo Catapano, Claire Fenouillet-Béranger, François Andrieu, Fred Gaillard, Philippe Ferrari
2021	—	`conf`	MOS technology for quantum computing: recent progress and perspectives for scaling up. DRC Louis Hutin, Benoit Bertrand, Heimanu Niebojewski, Pierre-André Mortemousque, Mikaël Cassé, Gérard Billiot, Xavier Jehl, Romain Maurand, Matias Urdampilleta, Yann-Michel Niquet, S. De Franceschi, Tristan Meunier, Maud Vinet
2018	—	`conf`	Performance & reliability of 3D architectures (πfet, Finfet, Ωfet). IRPS Antoine Laurent, Xavier Garros, Sylvain Barraud, J. Pelloux-Prayer, Mikaël Cassé, Fred Gaillard, X. Federspiel, David Roy, E. Vincent, Gérard Ghibaudo
2017	J	`jnl`	Harmonic distortion analysis of triple gate SOI nanowire MOSFETS down to 100 K. Microelectron. Reliab. Bruna Cardoso Paz, Renan Trevisoli Doria, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot, Marcelo Antonio Pavanello
2017	—	`conf`	Precise EOT regrowth extraction enabling performance analysis of low temperature extension first devices. ESSDERC Jessy Micout, Quentin Rafhay, Xavier Garros, Mikaël Cassé, Jean Coignus, Luca Pasini, Cao-Minh Vincent Lu, Nils Rambal, Claire Fenouillet-Béranger, Laurent Brunet, G. Romano, R. Gassilloud, Perrine Batude, Maud Vinet, Gérard Ghibaudo
2016	—	`conf`	Analog performance of strained SOI nanowires down to 10K. ESSDERC Bruna Cardoso Paz, Marcelo Antonio Pavanello, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Maud Vinet, Olivier Faynot
2016	J	`jnl`	Drain current model for short-channel triple gate junctionless nanowire transistors. Microelectron. Reliab. Bruna Cardoso Paz, Mikaël Cassé, Sylvain Barraud, Gilles Reimbold, Olivier Faynot, F. Avila-Herrera, Antonio Cerdeira, Marcelo Antonio Pavanello
2015	—	`conf`	Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model. ESSDERC J. Pelloux-Prayer, Mikaël Cassé, François Triozon, Sylvain Barraud, Yann-Michel Niquet, J.-L. Rouviere, Olivier Faynot, Gilles Reimbold
2014	—	`conf`	FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration. ESSDERC Claire Fenouillet-Béranger, Bernard Previtali, Perrine Batude, Fabrice Nemouchi, Mikaël Cassé, Xavier Garros, Lucie Tosti, Nils Rambal, Dominique Lafond, Hugo Dansas, Luca Pasini, Laurent Brunet, Fabien Deprat, Magali Grégoire, M. Mellier, Maud Vinet
2014	—	`conf`	Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. ESSDERC François Andrieu, Mikaël Cassé, E. Baylac, P. Perreau, O. Nier, Denis Rideau, R. Berthelon, Franck Pourchon, A. Pofelski, Barbara De Salvo, C. Gallon, Vincent Mazzocchi, D. Barge, C. Gaumer, O. Gourhant, A. Cros, Vincent Barral, Rossella Ranica, Nicolas Planes, Walter Schwarzenbach, E. Richard, Emmanuel Josse, Olivier Weber, Franck Arnaud, Maud Vinet, Olivier Faynot, Michel Haond
2013	—	`conf`	Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs. ESSDERC Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Gérard Ghibaudo, Hiroshi Iwai, Gilles Reimbold
2013	—	`conf`	Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations. ESSDERC Remi Coquand, Sylvain Barraud, Mikaël Cassé, Masahiro Koyama, Virginie Maffini-Alvaro, Marie-Pierre Samson, Lucie Tosti, Xavier Mescot, Gérard Ghibaudo, Stéphane Monfray, Frédéric Boeuf, Olivier Faynot, Barbara De Salvo
2012	—	`conf`	Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs. ESSDERC Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Hiroshi Iwai, Gérard Ghibaudo, Gilles Reimbold
2009	J	`jnl`	Process dependence of BTI reliability in advanced HK MG stacks. Microelectron. Reliab. Xavier Garros, Mikaël Cassé, M. Rafik, Claire Fenouillet-Béranger, Gilles Reimbold, François Martin, Claudia Wiemer, F. Boulanger