Mikaël Briday

25 papers A 2B 2C 6Misc 1Journal 5Unranked 9
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Study in Specification and Hardware Runtime Verification of Critical Embedded Software.
IEEE Trans. Dependable Secur. Comput.
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
2025 C conf
Circadia: Checkpointing for Intermittent Computing in AI Driven Applications.
DSD
Matthieu Rodet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
2024 B conf
EarlyBird: Energy belongs to those who wake up early.
RTCSA
Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
2024 A conf
SCHEMATIC: Compile-Time Checkpoint Placement and Memory Allocation for Intermittent Systems.
CGO
Hugo Reymond, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Isabelle Puaut, Erven Rohou
2023 J jnl
Cost-optimal timed trace synthesis for scheduling of intermittent embedded systems.
Discret. Event Dyn. Syst.
Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Olivier H. Roux
2023 J jnl
Design and verification of pipelined circuits with Timed Petri Nets.
Discret. Event Dyn. Syst.
Rémi Parrot, Mikaël Briday, Olivier H. Roux
2023 A conf
Securing a RISC-V architecture: A dynamic approach.
DATE
Sébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, Bertrand Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, André Sintzoff, Jean-Roch Coulon
2021 — conf
Energy Efficiency is Not Enough: Towards a Batteryless Internet of Sounds.
Audio Mostly Conference
Vincent Lostanlen, Antoine Bernabeu, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Mathieu Lagrange
2021 C conf
Pipeline Optimization using a Cost Extension of Timed Petri Nets.
ARITH
Rémi Parrot, Mikaël Briday, Olivier H. Roux
2021 B conf
Timed Petri Nets with Reset for Pipelined Synchronous Circuit Design.
Petri Nets
Rémi Parrot, Mikaël Briday, Olivier H. Roux
2018 — conf
HW-based Architecture for Runtime Verification of Embedded Software on SoPC systems.
AHS
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday
2018 Misc conf
Hardware Runtime Verification of a RTOS Kernel: Evaluation Using Fault Injection.
EDCC
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
2017 C conf
WCET Analysis by Model Checking for a Processor with Dynamic Branch Prediction.
VECoS
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
2016 — conf
BEST: a Binary Executable Slicing Tool.
WCET
Armel Mangean, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou
2016 — conf
Hardware runtime verification of embedded software in SoPC.
SIES
Dimitry Solet, Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Sébastien Pillement
2014 — conf
Improving processor hardware compiled cycle accurate simulation using program abstraction.
SimuTools
Adrien Bullich, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet
2014 C conf
Reactive embedded device driver synthesis using logical timed models.
SIMULTECH
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Olivier H. Roux
2013 C conf
Device driver synthesis for embedded systems.
ETFA
Julien Tanguy, Jean-Luc Béchennec, Mikaël Briday, Sebastien Dube, Olivier H. Roux
2012 J jnl
Harmless, a hardware architecture description language dedicated to real-time embedded system simulation.
J. Syst. Archit.
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Guillaume Savaton, Yvon Trinquet
2011 J jnl
An Architecture Description Language for Embedded Hardware Platforms.
Electron. Commun. Eur. Assoc. Softw. Sci. Technol.
Guillaume Savaton, Jean-Luc Béchennec, Mikaël Briday, Rola Kassem
2011 — conf
Extending Harmless architecture description language for embedded real-time systems validation.
SIES
Jean-Luc Béchennec, Mikaël Briday, Valere Alibert
2010 — conf
ViPER: a lightweight approach to the simulation of distributed and embedded software.
SimuTools
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Florent Pavin, Fabien Juif
2009 — conf
Instruction set simulator generation using HARMLESS, a new hardware architecture description language.
SimuTools
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
2008 — conf
Simulator generation using an automaton based pipeline model for timing analysis.
IMCSIT
Rola Kassem, Mikaël Briday, Jean-Luc Béchennec, Yvon Trinquet, Guillaume Savaton
2006 C conf
Trampoline An Open Source Implementation of the OSEK/VDX RTOS Specification.
ETFA
Jean-Luc Béchennec, Mikaël Briday, Sébastien Faucou, Yvon Trinquet