Mihir R. Choudhury

28 papers A* 3A 10B 1Misc 2Journal 9Unranked 3

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Agent Factories for High Level Synthesis: How Far Can General-Purpose Coding Agents Go in Hardware Optimization? CoRR Abhishek Bhandwaldar, Mihir R. Choudhury, Ruchir Puri, Akash Srivastava
2021	—	`conf`	CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. NeurIPS Datasets and Benchmarks Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Shyam Ramji, Ulrich Finkler, Susan Malaika, Frederick Reiss
2021	J	`jnl`	Project CodeNet: A Large-Scale AI for Code Dataset for Learning a Diversity of Coding Tasks. CoRR Ruchir Puri, David S. Kung, Geert Janssen, Wei Zhang, Giacomo Domeniconi, Vladimir Zolotov, Julian Dolby, Jie Chen, Mihir R. Choudhury, Lindsey Decker, Veronika Thost, Luca Buratti, Saurabh Pujar, Ulrich Finkler
2019	J	`jnl`	NeuNetS: An Automated Synthesis Engine for Neural Network Design. CoRR Atin Sood, Benjamin Elder, Benjamin Herta, Chao Xue, Costas Bekas, A. Cristiano I. Malossi, Debashish Saha, Florian Scheidegger, Ganesh Venkataraman, Gegi Thomas, Giovanni Mariani, Hendrik Strobelt, Horst Samulowitz, Martin Wistuba, Matteo Manica, Mihir R. Choudhury, Rong Yan, Roxana Istrate, Ruchir Puri, Tejaswini Pedapati
2016	J	`jnl`	Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2015	—	`conf`	Polynomial time algorithm for area and power efficient adder synthesis in high-performance designs. ASP-DAC Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2014	A	`conf`	Bridging high performance and low power in processor design. ISLPED Ruchir Puri, Mihir R. Choudhury, Haifeng Qian, Matthew M. Ziegler
2014	J	`jnl`	Time-Borrowing Circuit Designs and Hardware Prototyping for Timing Error Resilience. IEEE Trans. Computers Mihir R. Choudhury, Vikas Chandra, Robert C. Aitken, Kartik Mohanram
2014	J	`jnl`	Towards Optimal Performance-Area Trade-Off in Adders by Synthesis of Parallel Prefix Structures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2013	J	`jnl`	Low Cost Concurrent Error Masking Using Approximate Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mihir R. Choudhury, Kartik Mohanram
2013	A*	`conf`	Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. DAC Subhendu Roy, Mihir R. Choudhury, Ruchir Puri, David Z. Pan
2011	A	`conf`	Reliability-driven don't care assignment for logic synthesis. DATE Andrew Zukoski, Mihir R. Choudhury, Kartik Mohanram
2010	A	`conf`	Analytical model for TDDB-based performance degradation in combinational logic. DATE Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
2010	A	`conf`	Bi-decomposition of large Boolean functions using blocking edge graphs. ICCAD Mihir R. Choudhury, Kartik Mohanram
2010	—	`conf`	Dominant critical gate identification for power and yield optimization in logic circuits. ACM Great Lakes Symposium on VLSI Mihir R. Choudhury, Masoud Rostami, Kartik Mohanram
2010	A	`conf`	TIMBER: Time borrowing and error relaying for online timing error resilience. DATE Mihir R. Choudhury, Vikas Chandra, Kartik Mohanram, Robert C. Aitken
2009	A	`conf`	Masking timing errors on speed-paths in logic circuits. DATE Mihir R. Choudhury, Kartik Mohanram
2009	J	`jnl`	Reliability Analysis of Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Mihir R. Choudhury, Kartik Mohanram
2009	J	`jnl`	Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion. J. Electron. Test. Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
2009	A*	`conf`	Timing-driven optimization using lookahead logic circuits. DAC Mihir R. Choudhury, Kartik Mohanram
2008	A	`conf`	Approximate logic circuits for low overhead, non-intrusive concurrent error detection. DATE Mihir R. Choudhury, Kartik Mohanram
2008	A*	`conf`	Technology exploration for graphene nanoribbon FETs. DAC Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik Mohanram
2008	B	`conf`	Tunable Transient Filters for Soft Error Rate Reduction in Combinational Circuits. ETS Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
2007	A	`conf`	Accurate and scalable reliability analysis of logic circuits. DATE Mihir R. Choudhury, Kartik Mohanram
2007	A	`conf`	Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory. DATE Mihir R. Choudhury, Kyle Ringgenberg, Scott Rixner, Kartik Mohanram
2006	Misc	`conf`	Design Optimization for Robustness to Single Event Upsets. VTS Quming Zhou, Mihir R. Choudhury, Kartik Mohanram
2006	A	`conf`	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ICCAD Mihir R. Choudhury, Quming Zhou, Kartik Mohanram
2005	Misc	`conf`	Multiple Fault Testing of Logic Resources of SRAM-Based FPGAs. VLSI Design Saurabh Goyal, Mihir R. Choudhury, S. S. S. P. Rao, L. Kalyan Kumar