Miguel Arias-Estrada

29 papers B 3C 1Journal 8Unranked 17
YearRankTypeTitle / Venue / Authors
2019 J jnl
An FPGA 2D-convolution unit based on the CAPH language.
J. Real Time Image Process.
Abiel Aguilar-González, Miguel Arias-Estrada, Madaín Pérez Patricio, Jorge-Luis Camas-Anzueto
2019 J jnl
Depth from a Motion Algorithm and a Hardware Architecture for Smart Cameras.
Sensors
Abiel Aguilar-González, Miguel Arias-Estrada, François Berry
2019 J jnl
The fastest visual ego-motion algorithm in the west.
Microprocess. Microsystems
Abiel Aguilar-González, Miguel Arias-Estrada, François Berry, Juan Antonio de Jesús Osuna-Coutiño
2019 — conf
Towards Embedded Heterogeneous FPGA-GPU Smart Camera Architectures for CNN Inference.
ICDSC
Walther Carballo-Hernández, François Berry, Maxime Pelcat, Miguel Arias-Estrada
2018 J jnl
Robust feature extraction algorithm suitable for real-time embedded applications.
J. Real Time Image Process.
Abiel Aguilar-González, Miguel Arias-Estrada, François Berry
2017 — conf
Camera Pose Estimation Suitable for Smart Cameras.
ICDSC
Abiel Aguilar-González, Miguel Arias-Estrada, François Berry
2017 — conf
Deep Learning Pulsed-based Convolutional Neuroprocessor Architecture on FPGAs.
ICDSC
Walther Carballo-Hernández, Miguel Arias-Estrada
2017 — conf
Dense Feature Matching Core for FPGA-based Smart Cameras.
ICDSC
Abiel Aguilar-González, Miguel Arias-Estrada, François Berry
2017 — conf
GPU-based Visual Odometry for Autonomous Vehicle Applications.
ICDSC
Juan Antonio de Jesús Osuna-Coutiño, Abiel Aguilar-González, Miguel Arias-Estrada
2017 J jnl
Improving visual vocabularies: a more discriminative, representative and compact bag of visual words.
Informatica (Slovenia)
Leonardo Chang, Airel Pérez Suárez, José Hernández-Palancar, Miguel Arias-Estrada, Luis Enrique Sucar
2012 — conf
Embedded attitude control system for the educative satellite SATEDU.
CONIELECOMP
Mario Alberto Mendoza-Barcenas, Eduardo Vizcaino Torres, Esaú Vicente-Vivas, Miguel Arias-Estrada, Ignacio Mendoza Nucamendi, Jose Angel Colin Robles
2010 J jnl
Population Coding and SpikeProp Hardware Accelerator for Spiking Neural Networks.
Res. Comput. Sci.
César Torres-Huitzil, Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada
2009 — conf
Hardware/Software FPGA Architecture for Robotics Applications.
ARC
Juan Carlos Moctezuma Eugenio, Miguel Arias-Estrada
2008 — conf
A Low-Level Image Processing Algorithms Accelerator Platform.
CONIELECOMP
Griselda Saldaña, Miguel Arias-Estrada
2008 C conf
Ranking Corner Points by the Angular Difference between Dominant Edges.
ICVS
Rafael Lemuz-López, Miguel Arias-Estrada
2007 — conf
Compact FPGA-based systolic array architecture suitable for vision systems.
ITNG
Griselda Saldaña, Miguel Arias-Estrada
2007 J jnl
Compact FPGA-based systolic array architecture suitable for vision systems.
Int. J. High Perform. Syst. Archit.
Griselda Saldaña, Miguel Arias-Estrada
2006 — conf
A Domain Reduction Algorithm for Incremental Projective Reconstruction.
ISVC (2)
Rafael Lemuz-López, Miguel Arias-Estrada
2006 — conf
Customizable FPGA-based architecture for video applications in real time.
FPT
Griselda Saldaña, Miguel Arias-Estrada
2006 — conf
Iterative Closest SIFT Formulation for Robust Feature Matching.
ISVC (2)
Rafael Lemuz-López, Miguel Arias-Estrada
2006 — conf
Real Time FPGA-based Architecture for Video Applications.
ReConFig
Griselda Saldaña, Miguel Arias-Estrada
2005 — conf
3D Recovery with Free Hand Camera Motion.
ENC
Gerardo Sosa-Ramirez, Miguel Arias-Estrada
2005 — conf
FPGA-based customizable systolic architecture for image processing applications.
ReConFig
Griselda Saldaña, Miguel Arias-Estrada
2005 — conf
Super-resolution with integrated radial distortion correction.
ENC
Liz Castillo-Jimenez, Miguel Arias-Estrada
2003 J jnl
Arquitectura hardware para el seguimiento de objetos utilizando procesamiento piramidal.
Res. Comput. Sci.
Marco Aurelio Nuño-Maganda, Miguel Arias-Estrada
2003 B conf
FPGA Based High Density Spiking Neural Network Array.
FPL
Juan M. Xicoténcatl Pérez, Miguel Arias-Estrada
2002 B conf
An FPGA Co-processor for Real-Time Visual Tracking.
FPL
Miguel Arias-Estrada, Eduardo Rodríguez-Palacios
2001 B conf
Multiple Stereo Matching Using an Extended Architecture.
FPL
Miguel Arias-Estrada, Juan M. Xicoténcatl Pérez
2000 — conf
Bragg Curve Identification Using a Neural Network.
IJCNN (4)
Juan Jaime Vega, M. Rocio Reynoso, Miguel Arias-Estrada, Leopoldo Altamirano Robles