Michitaka Kameyama

222 papers A* 3A 3B 3C 6Misc 1Journal 122Unranked 84
YearRankTypeTitle / Venue / Authors
2025 J jnl
Synthetic Data-Based Algorithm Selection for Medical Image Classification Under Limited Data Availability.
Algorithms
Maxim Zhabinets, Benjamin Tyler, Martin Lukac, Shinobu Nagayama, Ferdinand Molnár, Michitaka Kameyama
2024 J jnl
Geometric Refactoring of Quantum and Reversible Circuits Using Graph Algorithms.
IEICE Trans. Inf. Syst.
Martin Lukac, Saadat Nursultan, Georgiy Krylov, Oliver Keszöcze, Abilmansur Rakhmettulayev, Michitaka Kameyama
2024 — conf
Ternary Function Classification Using Machine Learning.
ISMVL
Martin Lukac, Krzysztof Podlaski, Shinobu Nagayama, Michitaka Kameyama
2023 — conf
Verification Based Algorithm Selection.
IDT
Martin Lukac, Michitaka Kameyama
2022 — conf
Approximate Function Classification.
ICCS (1)
Martin Lukac, Krzysztof Podlaski, Michitaka Kameyama
2021 J jnl
Optimization of LNN Reversible Circuits Using an Analytic Sifting Method.
J. Circuits Syst. Comput.
Martin Lukac, Pawel Kerntopf, Michitaka Kameyama
2020 — conf
Selecting Algorithms Without Meta-features.
ICPR Workshops (4)
Martin Lukac, Ayazkhan Bayanov, Albina Li, Kamila Abdiyeva, Nadira Izbassarova, Magzhan Gabidolla, Michitaka Kameyama
2018 — conf
CNOT-Measure Quantum Neural Networks.
ISMVL
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
2018 B conf
High-Accuracy Scene Recognition and Its Application to Highly-Safe Intelligent Systems.
SMC
Kenichi Takada, Michitaka Kameyama
2017 J jnl
Building a Completely Reversible Computer.
CoRR
Martin Lukac, Gerhard W. Dueck, Michitaka Kameyama, Anirban Pathak
2017 J jnl
Context Based Visual Content Verification.
CoRR
Martin Lukac, Aigerim Bazarbayeva, Michitaka Kameyama
2017 — conf
Fine-Grain Pipelined Reconfigurable VLSI Architecture Based on Multiple-Valued Multiplexer Logic.
ISMVL
Katsuhiko Shimabukuro, Michitaka Kameyama
2017 B conf
Live-feeling communication: Multi-algorithm approach to the estimation of human intentions.
SMC
Martin Lukac, Michitaka Kameyama, Yevgeniya Migranova
2016 J jnl
On Minimal Accuracy Algorithm Selection in Computer Vision and Intelligent Systems.
CoRR
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
2016 J jnl
Reasoning and Algorithm Selection Augmented Symbolic Segmentation.
CoRR
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
2015 J jnl
An algorithm selection based platform for image understanding using high-level symbolic feedback and machine learning.
Int. J. Mach. Learn. Cybern.
Martin Lukac, Michitaka Kameyama
2015 J jnl
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path.
IEEE Trans. Very Large Scale Integr. Syst.
Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama
2015 J jnl
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2015 — conf
Novel VLSI Architectures for Real-World Intelligent Systems.
ISMVL
Michitaka Kameyama
2015 J jnl
Symbolic Segmentation Using Algorithm Selection.
CoRR
Martin Lukac, Kamila Abdiyeva, Michitaka Kameyama
2014 — conf
Analysis of Faults in Reversible Computing.
ISMVL
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf, Claudio Moraga
2014 — conf
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme.
ISMVL
Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka
2014 — conf
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing.
APCCAS
Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama
2014 J jnl
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation.
J. Comput. Eng.
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama
2014 J jnl
Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a Low-Power Fine-Grain Reconfigurable VLSI.
IEICE Trans. Electron.
Xu Bai, Michitaka Kameyama
2014 C conf
Minimizing Reversible Circuits in the 2n Scheme Using Two and Three Bits Patterns.
DSD
Martin Lukac, Maher Hawash, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf
2014 J jnl
Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network.
IEICE Trans. Inf. Syst.
Xu Bai, Michitaka Kameyama
2014 J jnl
Reversible, Information-Preserving Logic and Its Application.
J. Multiple Valued Log. Soft Comput.
Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
2014 J jnl
Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams.
IEICE Trans. Inf. Syst.
Martin Lukac, Dipal Shah, Marek A. Perkowski, Michitaka Kameyama
2013 J jnl
A Bit-Serial Reconfigurable VLSI Based on a Multiple-Valued X-Net Data Transfer Scheme.
IEICE Trans. Inf. Syst.
Xu Bai, Michitaka Kameyama
2013 J jnl
A Multiple-Valued Reconfigurable VLSI Architecture Using Binary-Controlled Differential-Pair Circuits.
IEICE Trans. Electron.
Xu Bai, Michitaka Kameyama
2013 — conf
An Area-Efficient Multiple-Valued Reconfigurable VLSI Architecture Using an X-Net.
ISMVL
Xu Bai, Michitaka Kameyama
2013 — conf
Analysis of Reversible and Quantum Finite State Machines Using Homing, Synchronizing and Distinguishing Input Sequences.
ISMVL
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski, Pawel Kerntopf
2013 J jnl
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design.
IEICE Trans. Inf. Syst.
Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2013 — conf
Bayesian Network for algorithm selection: Real-world hierarchy for nodes reduction.
iCAST/UMEDIA
Martin Lukac, Michitaka Kameyama
2013 J jnl
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2013 J jnl
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures.
J. Multiple Valued Log. Soft Comput.
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2013 — conf
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment.
EMBC
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2013 — conf
Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply Voltages for a Reconfigurable VLSI.
ISMVL
Xu Bai, Michitaka Kameyama
2013 — conf
Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification (XQS) Format.
ISMVL
Maher Hawash, Martin Lukac, Michitaka Kameyama, Marek A. Perkowski
2013 — conf
Natural image understanding using algorithm selection and high-level feedback.
Intelligent Robots and Computer Vision: Algorithms and Techniques
Martin Lukac, Michitaka Kameyama, Kosuke Hiura
2013 J jnl
Quantum Finite State Machines - a Circuit Based Approach.
Int. J. Unconv. Comput.
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski
2013 J jnl
RFID-based localization with Non-Blocking tag scanning.
Ad Hoc Networks
Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama
2012 J jnl
A Digit-Serial Reconfigurable VLSI Based on Quaternary Inter-Cell Data Transfer Scheme.
J. Multiple Valued Log. Soft Comput.
Xu Bai, Nobuaki Okada, Michitaka Kameyama
2012 J jnl
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation.
IEICE Trans. Electron.
Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama
2012 — conf
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme.
ISOCC
Yoshichika Fujioka, Michitaka Kameyama
2012 — conf
Current-Source-Sharing Differential-Pair Circuits for a Low-Power Fine-Grain Reconfigurable VLSI Architecture.
ISMVL
Xu Bai, Michitaka Kameyama
2012 J jnl
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates.
IEICE Trans. Electron.
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2012 J jnl
Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe Intelligent Vehicle.
J. Robotics Mechatronics
Bo Sun, Michitaka Kameyama
2012 C conf
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit.
ISCAS
Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2012 C conf
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators.
ISCAS
Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama
2012 J jnl
High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level Parallelization vs. Representation?
J. Multiple Valued Log. Soft Comput.
Martin Lukac, Michitaka Kameyama, D. Michael Miller, Marek A. Perkowski
2012 J jnl
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors.
IEICE Trans. Inf. Syst.
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
2012 — conf
Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial Circuits.
ISMVL
Shogo Kisara, Michitaka Kameyama
2011 J jnl
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating.
IEEE Trans. Very Large Scale Integr. Syst.
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011 J jnl
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing.
Inf. Media Technol.
Kan Watanabe, Masaru Fukushi, Michitaka Kameyama
2011 J jnl
Adaptive Group-Based Job Scheduling for High Performance and Reliable Volunteer Computing.
J. Inf. Process.
Kan Watanabe, Masaru Fukushi, Michitaka Kameyama
2011 — conf
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture.
ASP-DAC
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2011 J jnl
Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits Embedded in Ternary Quantum Space using Heuristics
CoRR
Maarti nLukac, Marek A. Perkowski, Michitaka Kameyama
2011 — conf
High Performance Tag Singulation for Memory-Less RFID Systems.
ICC
Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama
2011 J jnl
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture.
IEICE Trans. Electron.
Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2011 — conf
Information-Preserving Logic Based on Logical Reversibility to Reduce the Memory Data Transfer Bottleneck and Heat Dissipation.
ISMVL
Martin Lukac, Ben Shuai, Michitaka Kameyama, D. Michael Miller
2011 J jnl
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors.
IEEE Trans. Circuits Syst. Video Technol.
Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama
2011 J jnl
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2011 C conf
Non-blocking tag scanning for passive RFID localization.
ISDA
Keyvan Kashkouli Nejad, Xiaohong Jiang, Michitaka Kameyama
2010 J jnl
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals.
IEICE Trans. Inf. Syst.
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2010 Misc conf
Adaptive Selection of Intelligent Processing Modules and its Applications.
IC-AI
Martin Lukac, Michitaka Kameyama, Marek A. Perkowski
2010 J jnl
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture.
IEICE Trans. Electron.
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2010 — conf
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture.
ERSA
Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama
2010 — conf
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores.
ERSA
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2010 B conf
Evolutionary quantum logic synthesis of Boolean reversible logic circuits embedded in ternary quantum space using structural restrictions.
IEEE Congress on Evolutionary Computation
Martin Lukac, Marek A. Perkowski, Michitaka Kameyama
2010 J jnl
Foreword.
IEICE Trans. Inf. Syst.
Michitaka Kameyama
2010 J jnl
Group Testing Based Detection of Web Service DDoS Attackers.
IEICE Trans. Commun.
Dalia Nashat, Xiaohong Jiang, Michitaka Kameyama
2010 J jnl
Logic-In-Control-Architecture-Based Reconfigurable VLSI Using Multiple-Valued Differential-Pair Circuits.
IEICE Trans. Inf. Syst.
Nobuaki Okada, Michitaka Kameyama
2010 — conf
Low-Power Multiple-Valued Reconfigurable VLSI Based on Superposition of Bit-Serial Data and Current-Source Control Signals.
ISMVL
Akitaka Ishikawa, Nobuaki Okada, Michitaka Kameyama
2010 — conf
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time.
ERSA
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
2010 J jnl
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama
2009 — conf
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic.
ERSA
Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama
2009 — conf
A low-power FPGA based on autonomous fine-grain power-gating.
ASP-DAC
Shota Ishihara, Masanori Hariyama, Michitaka Kameyama
2009 — conf
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays.
ERSA
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2009 — conf
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters.
ERSA
Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama
2009 — conf
Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture.
ISMVL
Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama
2009 — conf
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation.
ERSA
Masanori Hariyama, Keita Tanji, Michitaka Kameyama
2009 J jnl
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture.
IEICE Trans. Electron.
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2009 — conf
Multiple-Valued Reconfigurable VLSI Processor Based on Superposition of Data and Control Signals.
ISMVL
Nobuaki Okada, Michitaka Kameyama
2009 J jnl
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows.
IEEE Trans. Very Large Scale Integr. Syst.
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
2008 J jnl
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling.
IEICE Trans. Electron.
Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama
2008 J jnl
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2008 J jnl
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture.
IEICE Trans. Electron.
Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
2008 A conf
FPGA implementation of a vehicle detection algorithm using three-dimensional information.
IPDPS
Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama
2008 J jnl
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits and Its Evaluation.
IEICE Trans. Electron.
Nobuaki Okada, Michitaka Kameyama
2008 — conf
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells.
ISMVL
Nobuaki Okada, Michitaka Kameyama
2008 — conf
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning.
ERSA
Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama
2008 J jnl
Memory Allocation for Multi-Resolution Image Processing.
IEICE Trans. Inf. Syst.
Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama
2008 J jnl
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment.
IEICE Trans. Electron.
Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
2008 — conf
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
ERSA
Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
2007 — conf
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.
ISMVL
Nobuaki Okada, Michitaka Kameyama
2007 J jnl
Low-Power Multiple-Valued Reconfigurable VLSI Using Series-Gating Differential-Pair Circuits.
J. Multiple Valued Log. Soft Comput.
Nobuaki Okada, Michitaka Kameyama
2007 J jnl
Special Section on VLSI Technology toward Frontiers of New Market.
IEICE Trans. Electron.
Michitaka Kameyama
2007 — conf
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation.
ISMVL
Tasuku Ito, Michitaka Kameyama
2007 J jnl
Universal VLSI Based on a Redundant Multiple-Valued Sequential Logic Operation.
J. Multiple Valued Log. Soft Comput.
Tasuku Ito, Michitaka Kameyama
2006 J jnl
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates.
IEICE Trans. Electron.
Masanori Hariyama, Sho Ogata, Michitaka Kameyama
2006 — conf
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment.
APCCAS
Masanori Hariyama, Michitaka Kameyama
2006 A conf
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal.
IPDPS
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
2006 — conf
Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip Architecture.
ISMVL
Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
2006 — conf
Fine-Grain Cell Design for Multiple-Valued Reconfigurable VLSI Using a Single Differential-Pair Circuit.
ISMVL
Haque Mohammad Munirul, Michitaka Kameyama
2006 — conf
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design.
APCCAS
W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama
2006 J jnl
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification.
IEICE Trans. Electron.
Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama
2006 — conf
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors.
ISVLSI
Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi
2006 — conf
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals.
ISMVL
Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama
2005 A conf
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory.
IPDPS
Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama
2005 J jnl
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access.
IEICE Trans. Inf. Syst.
Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama
2005 J jnl
Design of a Low-Power Multiple-Valued Integrated Circuit Based on Dynamic Source-Coupled Logic.
J. Multiple Valued Log. Soft Comput.
Akira Mochizuki, Takahiro Hanyu, Michitaka Kameyama
2005 J jnl
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama
2005 J jnl
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages.
IEEE Trans. Computers
Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama
2005 — conf
Implementation and Evaluation of a Fine-Grain Multiple-Valued Field Programmable VLSI Based on Source-Coupled Logic.
ISMVL
Haque Mohammad Munirul, Tomoaki Hasegawa, Michitaka Kameyama
2005 J jnl
Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.
J. Multiple Valued Log. Soft Comput.
Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama
2005 J jnl
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
2005 J jnl
Multiple-Valued Logic as a New Computing Paradigm - A Brief Survey of Higuchi's Researchon Multiple-Valued Logic.
J. Multiple Valued Log. Soft Comput.
Michitaka Kameyama, Takahiro Hanyu, Takafumi Aoki
2005 — conf
Multiple-Valued VLSI Architecture for Intra-Chip Packet Data Transfer.
ISMVL
Tomoaki Hasegawa, Yuya Homma, Michitaka Kameyama
2005 — conf
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs.
ISVLSI
Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama
2005 — conf
VLSI architecture based on packet data transfer scheme and its application.
ISCAS (2)
Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi
2004 J jnl
Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI.
IEEE J. Solid State Circuits
Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
2004 — conf
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits.
ISVLSI
Weisheng Chong, Masanori Hariyama, Michitaka Kameyama
2004 — conf
Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and Its Applications.
ISMVL
Haque Mohammad Munirul, Michitaka Kameyama
2004 — conf
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure.
ISVLSI
Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama
2004 — conf
Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic.
ISMVL
Haque Mohammad Munirul, Michitaka Kameyama
2003 — conf
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic.
ISMVL
Takahiro Hanyu, Tomohiro Takahashi, Michitaka Kameyama
2003 — conf
Multiple-Valued Dynamic Source-Coupled Logic.
ISMVL
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
2003 J jnl
Multiple-Valued Logic-in-Memory VLSI Using MFSFETs and its Applications.
J. Multiple Valued Log. Soft Comput.
Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
2003 J jnl
Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated Circuit Based on Voltage Swing Minimization.
J. Multiple Valued Log. Soft Comput.
Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
2002 — conf
Fully Source-Coupled Logic Based Multiple-Valued VLSI.
ISMVL
Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
2002 — conf
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.
ISVLSI
Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama
2002 — conf
Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.
ISMVL
Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama
2001 — conf
Dual-Rail Multiple-Valued Current-Mode VLSI with Biasing Current Sources.
ISMVL
Tsukasa Ike, Takahiro Hanyu, Michitaka Kameyama
2001 — conf
Multiple-Valued Mask-Programmable Logic Array Using One-Transistor Universal-Literal Circuits.
ISMVL
Takahiro Hanyu, Michitaka Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran
2001 A* conf
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection.
ICRA
Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama
2000 J jnl
Architecture of a high-performance stereo vision VLSI processor.
Adv. Robotics
Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama
2000 — conf
Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.
ISMVL
Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama
2000 — conf
DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.
ISMVL
Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
2000 J jnl
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction.
J. Robotics Mechatronics
Hideki Kazama, Masanori Hariyama, Michitaka Kameyama
2000 J jnl
Editorial: Intelligent Integrated Systems for Human-Oriented Information Society.
J. Robotics Mechatronics
Michitaka Kameyama
2000 C conf
Integration of asynchronous and self-checking multiple-valued current-mode circuits based on dual-rail differential logic.
PRDC
Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
2000 — conf
Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.
ISMVL
Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
2000 J jnl
Path Planning Based on Distance Transformation and Its VLSI Implementation.
J. Robotics Mechatronics
Masanori Hariyama, Michitaka Kameyama
2000 J jnl
Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture.
J. Robotics Mechatronics
Masanori Hariyama, Michitaka Kameyama
1999 J jnl
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture.
Syst. Comput. Jpn.
Yoshichika Fujioka, Michitaka Kameyama
1999 — conf
Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor FETs.
ISMVL
Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama
1999 — conf
Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode Differential Logic.
ISMVL
Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama
1998 — conf
Asynchronous Multiple-Valued VLSI System Based on Dual-Rail Current-Mode Differential Logic.
ISMVL
Takahiro Hanyu, Takahiro Saito, Michitaka Kameyama
1998 J jnl
Design and evaluation of a digit-parallel multiple-valued content-addressable memory.
Syst. Comput. Jpn.
Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
1998 A* conf
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products.
ICRA
Masanori Hariyama, Michitaka Kameyama
1998 — conf
Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.
ISMVL
Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama
1998 J jnl
Optimal design of a current-mode deep-submicron multiple-valued integrated circuit and application.
Syst. Comput. Jpn.
Takahiro Saito, Takahiro Hanyu, Michitaka Kameyama
1997 J jnl
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects.
Syst. Comput. Jpn.
Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
1997 J jnl
Communication network protocol for real-time distributed control and its LSI implementation.
IEEE Trans. Ind. Electron.
Koji Kobayashi, Michitaka Kameyama, Tatsuo Higuchi
1997 — conf
Low-power multiple-valued current-mode integrated circuit with current-source control and its application.
ASP-DAC
Takahiro Hanyu, Satoshi Kazama, Michitaka Kameyama
1997 — conf
One-Transistor-Cell 4-Valued Universal-Literal CAM for Cellular Logic Image Processing.
ISMVL
Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
1996 J jnl
Author's Reply.
IEEE Trans. Computers
Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
1996 — conf
Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy.
ISMVL
Masami Nakajima, Michitaka Kameyama
1996 J jnl
Design of a one-transistor-cell multiple-valued CAM.
IEEE J. Solid State Circuits
Takahiro Hanyu, N. Kanagawa, Michitaka Kameyama
1996 J jnl
Design of a one-transistor-cell multiple-valued CAM.
IEEE J. Solid State Circuits
Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama
1996 J jnl
Editorial: Integration of Intelligence for Robotics in VLSI Chips.
J. Robotics Mechatronics
Michitaka Kameyama
1996 J jnl
Highly-Safe Intelligent Integrated Systems.
J. Robotics Mechatronics
Michitaka Kameyama
1996 J jnl
Optimal Design of a VLSI Processor with Spatially and Temporally Parallel Structure.
J. Robotics Mechatronics
Michitaka Kameyama, Masayuki Sasaki
1996 — conf
Quaternary Universal-Literal CAM for Cellular Logic Image Processing.
ISMVL
Takahiro Hanyu, Manabu Arakaki, Michitaka Kameyama
1996 J jnl
Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects.
J. Robotics Mechatronics
Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama
1996 J jnl
VLSI Processor System for Robotics.
J. Robotics Mechatronics
Michitaka Kameyama, Yoshichika Fujioka
1995 J jnl
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic.
IEEE J. Solid State Circuits
Takahiro Hanyu, Michitaka Kameyama
1995 — conf
Design of a Highly Parallel Multiple-Valued Linear Digital System for k-Ary Operations Based on Extended Representation Matrices.
ISMVL
M. Ryu, Michitaka Kameyama
1995 J jnl
Digital Control Parallel VLSI Processor.
J. Robotics Mechatronics
Michitaka Kameyama
1995 — conf
Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply Dual-Rail Source-Coupled Logic.
ISMVL
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
1995 — conf
Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital Systems.
ISMVL
Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama
1995 J jnl
Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super Pass Gate.
IEICE Trans. Inf. Syst.
Xiaowei Deng, Takahiro Hanyu, Michitaka Kameyama
1994 J jnl
Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles.
J. Robotics Mechatronics
Masanori Hariyama, Michitaka Kameyama
1994 J jnl
Coordinate Transformation VLSI Processor for Redundant Manipulator Control.
J. Robotics Mechatronics
Yoshichika Fujioka, Michitaka Kameyama, Tatsuo Higuchi
1994 — conf
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel
ISMVL
Masami Nakajima, Michitaka Kameyama
1994 J jnl
Design of a Model-Based Robot Vision VLSI Processor.
J. Robotics Mechatronics
Yoshifumi Sasaki, Michitaka Kameyama
1994 J jnl
Design of an Intelligent Fault-Tolerant System for Real-World Applications.
J. Robotics Mechatronics
Shigeki Abe, Michitaka Kameyama, Tatsuo Higuchi
1994 J jnl
Editorial: Intelligent Integrated Systems for Robotics.
J. Robotics Mechatronics
Michitaka Kameyama
1994 J jnl
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits.
IEEE Trans. Computers
Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
1994 J jnl
Latency Minimization of Parallel VLSI Processors for Robotics Using Integer Programming.
J. Robotics Mechatronics
Bumchul Kim, Michitaka Kameyama
1994 — conf
Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic.
ISMVL
Takahiro Hanyu, Akira Mochizuki, Michitaka Kameyama
1994 J jnl
Next-Generation Intelligent Integrated Systems Based on Multiple-Valued Digital Processing.
J. Robotics Mechatronics
Michitaka Kameyama
1993 — conf
2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control.
ICRA (3)
Yoshichika Fujioka, Michitaka Kameyama
1993 — conf
Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations.
ISMVL
Masami Nakajima, Michitaka Kameyama
1993 J jnl
Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations.
Syst. Comput. Jpn.
Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi
1992 — conf
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits.
ISMVL
Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi
1992 — conf
Design of a Multiple-Valued VLSI Processor for Digital Control.
ISMVL
Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi
1992 J jnl
Design of an ultrahigher-valued biocomputing system based on set-valued logic networks.
Syst. Comput. Jpn.
Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
1992 J jnl
Highly parallel collision detection processor for intelligent robots.
IEEE J. Solid State Circuits
Michitaka Kameyama, Tadao Amada, Tatsuo Higuchi
1992 J jnl
Interconnection-Free Biomolecular Computing.
Computer
Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
1992 — conf
Residue Arithmetic Based Multiple-Valued VLSI Image Processor.
ISMVL
Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi
1991 — conf
Design of Interconnection-Free Biomolecular Computing System.
ISMVL
Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi
1991 J jnl
Design of a robust fault-tolerant multiplier.
Syst. Comput. Jpn.
Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi
1991 C conf
High-Performance VLSI Processor for Robot Inverse Dynamics Computation.
ICCD
Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi
1991 J jnl
Performance evaluation of a multivalued rsa encryption vlsi.
Syst. Comput. Jpn.
Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi
1990 J jnl
Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model.
Syst. Comput. Jpn.
Michitaka Kameyama, Takafumi Aoki, Tatsuo Higuchi
1990 J jnl
Design of a Matrix Multiply-Addition VLSI Processor for Robot control.
J. Robotics Mechatronics
Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi
1990 J jnl
Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator.
J. Robotics Mechatronics
Tadao Amada, Michitaka Kameyama, Tatsuo Higuchi
1990 J jnl
Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation.
Syst. Comput. Jpn.
Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi
1990 J jnl
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits.
Syst. Comput. Jpn.
Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi
1990 J jnl
Editorial: Computer Architecture for Robotics.
J. Robotics Mechatronics
Michitaka Kameyama
1990 — conf
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System.
ISMVL
Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi
1990 J jnl
Multiple-valued radix-2 signed-digit arithmetic circuits for high-performance VLSI systems.
IEEE J. Solid State Circuits
Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi
1990 J jnl
Robot Electronics System.
J. Robotics Mechatronics
Tatsuo Higuchi, Michitaka Kameyama
1990 — conf
Toward the Age of Beyond-Binary Electronics and Systems.
ISMVL
Michitaka Kameyama
1989 J jnl
Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation.
Syst. Comput. Jpn.
Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
1989 J jnl
Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic.
IEEE J. Solid State Circuits
Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi
1989 A* conf
Implementation of a high performance LSI for inverse kinematics computation.
ICRA
Michitaka Kameyama, Takao Matsumoto, Hideki Egami, Tatsuo Higuchi
1989 J jnl
VLSI Computer for Robotics.
J. Robotics Mechatronics
Michitaka Kameyama, Tatsuo Higuchi
1988 J jnl
A 32*32-bit multiplier using multiple-valued MOS current-mode circuits.
IEEE J. Solid State Circuits
Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada
1988 J jnl
A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits.
Computer
Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi
1988 J jnl
Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System.
Syst. Comput. Jpn.
Michitaka Kameyama, Li Zheng, Tatsuo Higuchi
1988 J jnl
Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation.
Syst. Comput. Jpn.
Xi Yue Huang, Michitaka Kameyama, Tatsuo Higuchi
1987 J jnl
Design and implementation of an nmos image processor based on quaternary logic.
Syst. Comput. Jpn.
Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi
1987 J jnl
Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic.
Syst. Comput. Jpn.
Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi
1987 J jnl
Design of micropower CMOS quaternary memory circuits.
Syst. Comput. Jpn.
Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi
1986 J jnl
Design of low-power quaternary CMOS logic circuits.
Syst. Comput. Jpn.
Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi
1986 J jnl
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits.
Syst. Comput. Jpn.
Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi
1977 J jnl
Static-Hazard-Free
IEEE Trans. Computers
Tatsuo Higuchi, Michitaka Kameyama
1977 J jnl
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module.
IEEE Trans. Computers
Michitaka Kameyama, Tatsuo Higuchi