Michinobu Nakao

11 papers A 4Journal 2Unranked 5
YearRankTypeTitle / Venue / Authors
2013 J jnl
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs.
IEICE Trans. Electron.
Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko
2010 J jnl
Reduction of Area per Good Die for SoC Memory Built-In Self-Test.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
2008 — conf
Enhancing Transition Fault Model for Delay Defect Diagnosis.
ATS
Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake
2008 A conf
Hardware Overhead Reduction for Memory BIST.
ITC
Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
2002 A conf
Application of High-Quality Built-In Test to Industrial Designs.
ITC
Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
2002 — conf
At-Speed Built-in Test for Logic Circuits with Multiple Clocks.
Asian Test Symposium
Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
2001 — conf
Test Generation for Multiple-Threshold Gate-Delay Fault Model.
Asian Test Symposium
Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
2000 A conf
A BIST approach for very deep sub-micron (VDSM) defects.
ITC
Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo
1999 A conf
Low overhead test point insertion for scan-based BIST.
ITC
Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
1997 — conf
Accelerated Test Points Selection Method for Scan-Based BIST.
Asian Test Symposium
Michinobu Nakao, Kazumi Hatayama, Isao Higashi
1995 — conf
A parallel sequential test generation system DESCARTES based on real-valued logic simulation.
Asian Test Symposium
Hiroshi Date, Michinobu Nakao, Kazumi Hatayama