Michihiro Yamada

20 papers A 2C 2Journal 11Unranked 5

Year	Rank	Type	Title / Venue / Authors
2021	—	`conf`	Best Security Measures to Reduce Cyber-Incident and Data Breach Risks. DPM/CBT@ESORICS Hiroaki Kikuchi, Michihiro Yamada, Kazuki Ikegami, Koji Inui
2019	—	`conf`	Development of a Cyber Incident Information Crawler. IMIS Kazuki Ikegami, Michihiro Yamada, Hiroaki Kikuchi, Koji Inui
2019	C	`conf`	Mathematical Model to Estimate Loss by Cyber Incident in Japan. ICISSP Michihiro Yamada, Hiroaki Kikuchi, Naoki Matsuyama, Koji Inui
2018	C	`conf`	Evaluation and Development of Onomatopoeia CAPTCHAs. PST Michihiro Yamada, Riko Shigeno, Hiroaki Kikuchi, Maki Sakamoto
2017	—	`conf`	Decision Tree Analysis on Environmental Factors of Insider Threats. HCI (30) Michihiro Yamada, Koichi Niihara, Hiroaki Kikuchi
2017	—	`conf`	How Much is Risk Increased by Sharing Credential in Group? STM Hiroaki Kikuchi, Koichi Niihara, Michihiro Yamada
2017	—	`conf`	Sharing or Non-sharing Credentials: A Study of What Motivates People to Be Malicious Insiders. HCI (22) Koichi Niihara, Michihiro Yamada, Hiroaki Kikuchi
2001	J	`jnl`	Design methodology of embedded DRAM with virtual-socket architecture. IEEE J. Solid State Circuits Tadaaki Yamauchi, Mitsuya Kinoshita, Teruhiko Amano, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, Michihiro Yamada, Tsutomu Yoshihara
1999	J	`jnl`	A 5.3-GB/s embedded SDRAM core with slight-boost scheme. IEEE J. Solid State Circuits Akira Yamazaki, Tadato Yamagata, Makoto Hatakenaka, Atsushi Miyanishi, Isao Hayashi, Shigeki Tomishima, Atsuo Mangyo, Yoshio Yukinari, Takashi Tatsumi, Masashi Matsumura, Kazutami Arimoto, Michihiro Yamada
1999	J	`jnl`	Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada
1998	J	`jnl`	400-MHz random column operating SDRAM techniques with self-skew compensation. IEEE J. Solid State Circuits Takeshi Hamamoto, Masaki Tsukude, Kazutami Arimoto, Yasuhiro Konishi, Takayuki Miyamoto, Hideyuki Ozaki, Michihiro Yamada
1998	J	`jnl`	A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell. IEEE J. Solid State Circuits Hirotoshi Sato, Hideaki Nagaoka, Hiroaki Honda, Yukio Maki, Tomohisa Wada, Yutaka Arita, Kazuhito Tsutsumi, Makoto Taniguchi, Michihiro Yamada
1997	J	`jnl`	High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's. IEEE J. Solid State Circuits Takahiro Tsuruda, Mako Kobayashi, Masaki Tsukude, Tadato Yamagata, Kazutami Arimoto, Michihiro Yamada
1992	J	`jnl`	A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure. IEEE J. Solid State Circuits Tadato Yamagata, Masaaki Mihara, Takeshi Hamamoto, Yasumitsu Murai, Toshifumi Kobayashi, Michihiro Yamada, Hideyuki Ozaki
1991	J	`jnl`	A 45-ns 64-Mb DRAM with a merged match-line test architecture. IEEE J. Solid State Circuits Shigeru Mori, Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Kikuda, Makoto Suwa, Mitsuya Kinoshita, Atsushi Hachisuka, Hideaki Arima, Michihiro Yamada, Tsutomu Yoshihara, Shimpei Kayano
1991	A	`conf`	An Address Maskable Parallel Testing for Ultra High Density DRAMs. ITC Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada
1991	J	`jnl`	Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond. IEEE J. Solid State Circuits Shigeru Kikuda, Hiroshi Miyamoto, Shigeru Mori, Mitsutaka Niiro, Michihiro Yamada
1990	J	`jnl`	Improved address buffers, TTL input current reduction, and hidden refresh test mode in a 4-Mb DRAM. IEEE J. Solid State Circuits Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono, Ikuo Ogoh, Michihiro Yamada
1989	J	`jnl`	A 60-ns 3.3-V-only 16-Mbit DRAM with multipurpose register. IEEE J. Solid State Circuits Kazutami Arimoto, Kazuyasu Fujishima, Yoshio Matsuda, Masaki Tsukude, Tukasa Oishi, Wataru Wakamiya, Shin'ichi Satoh, Michihiro Yamada, Takao Nakano
1985	A	`conf`	Test Pattern Considerations for Fault Tolerant High Density DRAM. ITC Hiroshi Miyamoto, Koichiro Mashiko, Yoshikazu Morooka, Kazutami Arimoto, Michihiro Yamada, Takao Nakano