Michihiro Shintani

68 papers A* 1A 9B 1C 2Misc 4Journal 22Unranked 29

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Cryo-Compact Modeling Based on Sparse Gaussian Process. ASP-DAC Tetsuro Iwasaki, Takashi Sato, Michihiro Shintani
2025	—	`conf`	Cryo-HT: Hardware Trojan Activated at Cryogenic Temperatures. ASP-DAC Ayano Takaya, Ryuichi Nakajima, Jun Shiomi, Michihiro Shintani
2025	—	`conf`	Cryogenic Characterization and Compact Modeling of Forward Body-Bias Effects in 180nm Bulk CMOS Transistors. SOCC Zhipeng Liang, Shin Taniguchi, Hajime Takayama, Michihiro Shintani
2025	—	`conf`	Hardware Trojan Detection by Fine-grained Power Domain Partitioning. ASP-DAC Takahiro Ishikawa, Kose Yokooji, Yoshihiro Midoh, Noriyuki Miura, Michihiro Shintani, Jun Shiomi
2025	—	`conf`	Physics-based Modeling to Extend a MOSFET Compact Model for Cryogenic Operation. ASP-DAC Dondee Navarro, Shin Taniguchi, Chika Tanaka, Kazutoshi Kobayashi, Takashi Sato, Michihiro Shintani
2024	—	`conf`	(Invited) Redefining Outliers for On-Wafer Electrical Testing. MLCAD Michihiro Shintani, Takashi Sato
2024	A	`conf`	Accelerating Machine Learning-Based Memristor Compact Modeling Using Sparse Gaussian Process. DATE Yuta Shintani, Michiko Inoue, Michihiro Shintani
2024	A	`conf`	EcoFlex-HDP: High-Speed and Low-Power and Programmable Hyperdimensional-Computing Platform with CPU Co-Processing. DATE Yuya Isaka, Nau Sakaguchi, Michiko Inoue, Michihiro Shintani
2024	J	`jnl`	Efficient Wafer-Level Spatial Variation Modeling for Multi-Site RF IC Testing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michihiro Shintani
2024	Misc	`conf`	Square-Wave Defined Pulse Generator for High Fidelity Gate Operation of Superconducting Qubits. QCE Ryosuke Matsuo, Kazuhisa Ogawa, Hidehisa Shiorni, Makoto Negoro, Ryutaro Ohira, Takefumi Miyoshi, Michihiro Shintani, Hiromitsu Awano, Takashi Sato, Jun Shiomi
2024	J	`jnl`	Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani
2023	—	`conf`	Feasibility Study of Incremental Neural Network Based Test Escape Detection by Introducing Transfer Learning Technique. ITC-Asia Ayano Takaya, Michihiro Shintani
2023	A	`conf`	Improving Efficiency and Robustness of Gaussian Process Based Outlier Detection via Ensemble Learning. ITC Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Takashi Sato, Michihiro Shintani
2023	—	`conf`	Wafer-Level Characteristic Variation Modeling Considering Systematic Discontinuous Effects. ASP-DAC Takuma Nagao, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue, Michihiro Shintani
2022	A	`conf`	Accurate Failure Rate Prediction Based on Gaussian Process Using WAT Data. ITC Makoto Eiki, Tomoki Nakamura, Masuo Kajiyama, Michiko Inoue, Michihiro Shintani
2022	J	`jnl`	Adaptive Outlier Detection for Power MOSFETs Based on Gaussian Process Regression. CoRR Kyohei Shimozato, Michihiro Shintani, Takashi Sato
2022	J	`jnl`	Efficient Analysis for Mitigation of Workload-Dependent Aging Degradation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shumpei Morita, Song Bian, Michihiro Shintani, Takashi Sato
2022	J	`jnl`	Systematic Unsupervised Recycled Field-Programmable Gate Array Detection. CoRR Yuya Isaka, Michihiro Shintani, Foisal Ahmed, Michiko Inoue
2021	J	`jnl`	Accelerating Parameter Extraction of Power MOSFET Models Using Automatic Differentiation. CoRR Michihiro Shintani, Aoi Ueda, Takashi Sato
2021	J	`jnl`	Accurate Recycled FPGA Detection Using an Exhaustive-Fingerprinting Technique Assisted by WID Process Variation Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2021	J	`jnl`	Hardware-Software Co-Design for Decimal Multiplication. Comput. Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue
2021	—	`conf`	Robust Fault-Tolerant Design Based on Checksum and On-Line Testing for Memristor Neural Network. ATS Michihiro Shintani, Mamoru Ishizaka, Michiko Inoue
2021	A	`conf`	Study on High-Accuracy and Low-Cost Recycled FPGA Detection. ITC Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2021	C	`conf`	Unsupervised Recycled FPGA Detection Based on Direct Density Ratio Estimation. IOLTS Yuya Isaka, Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2021	A	`conf`	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. ITC Michihiro Shintani, Riaz-ul-haque Mian, Michiko Inoue, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki
2021	J	`jnl`	Wafer-level Variation Modeling for Multi-site RF IC Testing via Hierarchical Gaussian Process. CoRR Michihiro Shintani, Riaz-ul-haque Mian, Tomoki Nakamura, Masuo Kajiyama, Makoto Eiki, Michiko Inoue
2020	J	`jnl`	Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit. J. Electron. Test. Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue
2020	J	`jnl`	Cost-Efficient Recycled FPGA Detection through Statistical Performance Characterization Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2020	J	`jnl`	Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. CoRR Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue
2020	—	`conf`	Influence of Device Parameter Variability on Current Sharing of Parallel-Connected SiC MOSFETs. ATS Yohei Nakamura, Naotaka Kuroda, Atsushi Yamaguchi, Ken Nakahara, Michihiro Shintani, Takashi Sato
2020	—	`conf`	LBIST-PUF: An LBIST Scheme Towards Efficient Challenge-Response Pairs Collection and Machine-Learning Attack Tolerance Improvement. ATS Michihiro Shintani, Tomoki Mino, Michiko Inoue
2020	—	`conf`	Measurement of BTI-induced Threshold Voltage Shift for Power MOSFETs under Switching Operation. ATS Aoi Ueda, Michihiro Shintani, Michiko Inoue, Takashi Sato
2019	—	`conf`	Cycle-Accurate Evaluation of Software-Hardware Co-Design of Decimal Computation in RISC-V Ecosystem. SoCC Riaz-ul-haque Mian, Michihiro Shintani, Michiko Inoue
2019	B	`conf`	Feature Engineering for Recycled FPGA Detection Based on WID Variation Modeling. ETS Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2019	—	`conf`	Low Cost Recycled FPGA Detection Using Virtual Probe Technique. ITC-Asia Foisal Ahmed, Michihiro Shintani, Michiko Inoue
2018	—	`conf`	A study on NBTI-induced delay degradation considering stress frequency dependence. ISQED Zuitoku Shin, Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2018	—	`conf`	Area-Efficient and Reliable Hybrid CMOS/Memristor ECC Circuit for ReRAM Storage. ATS Mamoru Ishizaka, Michihiro Shintani, Michiko Inoue
2018	A	`conf`	Artificial Neural Network Based Test Escape Screening Using Generative Model. ITC Michihiro Shintani, Michiko Inoue, Yoshiyuki Nakamura
2018	—	`conf`	Decimal Multiplication Using Combination of Software and Hardware. APCCAS Mian Riaz-ul-haque, Michihiro Shintani, Michiko Inoue
2018	—	`conf`	Efficient worst-case timing analysis of critical-path delay under workload-dependent aging degradation. ASP-DAC Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2018	A	`conf`	Variation-Aware Hardware Trojan Detection through Power Side-channel. ITC Fakir Sharif Hossain, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
2017	—	`conf`	Comparative study of path selection and objective function in replacing NBTI mitigation logic. ISQED Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2017	J	`jnl`	Identification and Application of Invariant Critical Paths under NBTI Degradation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Song Bian, Shumpei Morita, Michihiro Shintani, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2017	—	`conf`	Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection. ATS Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
2017	A*	`conf`	LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. DAC Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2017	—	`conf`	Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. ASP-DAC Yu-Guang Chen, Michihiro Shintani, Takashi Sato, Yiyu Shi, Shih-Chieh Chang
2017	J	`jnl`	Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shumpei Morita, Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2016	J	`jnl`	Fast Estimation of NBTI-Induced Delay Degradation Based on Signal Probability. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato
2016	—	`conf`	Nonlinear delay-table approach for full-chip NBTI degradation prediction. ISQED Song Bian, Michihiro Shintani, Shumpei Morita, Masayuki Hiromoto, Takashi Sato
2016	J	`jnl`	Path Clustering for Test Pattern Reduction of Variation-Aware Adaptive Path Delay Testing. J. Electron. Test. Michihiro Shintani, Takumi Uezono, Kazumi Hatayama, Kazuya Masu, Takashi Sato
2016	—	`conf`	Runtime NBTI Mitigation for Processor Lifespan Extension via Selective Node Control. ATS Song Bian, Michihiro Shintani, Zheng Wang, Masayuki Hiromoto, Anupam Chattopadhyay, Takashi Sato
2016	—	`conf`	Workload-Aware Worst Path Analysis of Processor-Scale NBTI Degradation. ACM Great Lakes Symposium on VLSI Song Bian, Michihiro Shintani, Shumpei Morita, Hiromitsu Awano, Masayuki Hiromoto, Takashi Sato
2014	J	`jnl`	A Variability-Aware Adaptive Test Flow for Test Quality Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu, Takashi Sato
2014	J	`jnl`	IDDQ Outlier Screening through Two-Phase Approach: Clustering-Based Filtering and Estimation-Based Current-Threshold Determination. IEICE Trans. Inf. Syst. Michihiro Shintani, Takashi Sato
2014	A	`conf`	Sensorless estimation of global device-parameters based on F ICCAD Michihiro Shintani, Takashi Sato
2013	—	`conf`	An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ASP-DAC Michihiro Shintani, Takashi Sato
2013	J	`jnl`	Device-Parameter Estimation through IDDQ Signatures. IEICE Trans. Inf. Syst. Michihiro Shintani, Takashi Sato
2012	Misc	`conf`	A Bayesian-based process parameter estimation using IDDQ current signature. VTS Michihiro Shintani, Takashi Sato
2010	Misc	`conf`	Path clustering for adaptive test. VTS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2010	C	`conf`	Scan based process parameter estimation through path-delay inequalities. ISCAS Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
2009	—	`conf`	An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
2009	Misc	`conf`	Small Delay Fault Model for Intra-Gate Resistive Open Defects. VTS Masayuki Arai, Akifumi Suto, Kazuhiko Iwasaki, Katsuyuki Nakano, Michihiro Shintani, Kazumi Hatayama, Takashi Aikyo
2007	J	`jnl`	A Variable-Length Coding Adjustable for Compressed Test Application. IEICE Trans. Inf. Syst. Hideyuki Ichihara, Toshihiro Ohara, Michihiro Shintani, Tomoo Inoue
2006	J	`jnl`	An Adaptive Decompressor for Test Application with Variable-Length Coding. Inf. Media Technol. Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
2005	—	`conf`	A Huffman-based coding with efficient test application. ASP-DAC Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue
2005	J	`jnl`	Huffman-Based Test Response Coding. IEICE Trans. Inf. Syst. Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue
2004	—	`conf`	A Test Decompression Scheme for Variable-Length Coding. Asian Test Symposium Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
2003	—	`conf`	Test Response Compression Based on Huffman Coding. Asian Test Symposium Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue