Michihiro Koibuchi

195 papers A* 6A 7B 24C 24Misc 8Journal 62Unranked 62

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 590-Nanosecond 757-Gbps FPGA Lossy Compressed Network. IEEE Trans. Parallel Distributed Syst. Michihiro Koibuchi, Takumi Honda, Naoto Fukumoto, Shoichi Hirasawa, Koji Nakano
2025	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Michihiro Koibuchi
2025	J	`jnl`	In-network stable radix sorter using many FPGAs with high-bandwidth photonics [Invited]. J. Opt. Commun. Netw. Kenji Mizutani, Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Shigeru Nakamura, Tatsuya Usuki, Kiyo Ishii, Ryosuke Matsumoto, Takashi Inoue, Shu Namiki, Michihiro Koibuchi
2025	C	`conf`	Lossy Compressed Collective Inter-FPGA Communications. HPC Asia Michihiro Koibuchi, Yoshinobu Ishida, Shoichi Hirasawa, Yao Hu, Takumi Honda, Yusuke Nagasaka, Naoto Fukumoto
2025	J	`jnl`	Photonic Ising Machine Using Parallel Bandit Architecture Based on Laser Chaos. IEEE Access Ryota Yasudo, Michihiro Koibuchi, Mikio Hasegawa
2024	B	`conf`	A Bandwidth-Optimal All-to-All Communication in Two-Dimensional Fully Connected Network. CCGrid Kien Trung Pham, Truong Thao Nguyen, Michihiro Koibuchi
2024	—	`conf`	Performance of Radix Sort using All-to-all Optical Interconnection Network in an Eight-FPGA Cluster. OFC Kenji Mizutani, Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Shigeru Nakamura, Tatsuya Usuki, Kiyo Ishii, Ryosuke Matsumoto, Takashi Inoue, Shu Namiki, Michihiro Koibuchi
2024	—	`conf`	The Case for Coherence Directories in Memory Cubes. MCSoC Yuki Kameyama, Naoya Niwa, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2023	J	`jnl`	A Case for Offloading Federated Learning Server on Smart NIC. CoRR Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani
2023	J	`jnl`	A Compression Router for Low-Latency Network-on-Chip. IEICE Trans. Inf. Syst. Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi
2023	C	`conf`	An Auto-Tuning Method for High-Bandwidth Low-Latency Approximate Interconnection Networks. PDP Shoichi Hirasawa, Michihiro Koibuchi
2023	J	`jnl`	Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. Ryota Yasudo, Koji Nakano, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2023	J	`jnl`	Effective switchless inter-FPGA memory networks. J. Parallel Distributed Comput. Truong Thao Nguyen, Kien Trung Pham, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi
2023	J	`jnl`	Experimental Demonstration of Approximate Communication Based on Radio-Over- Fiber Systems. IEEE Access Toshiki Ishimaru, Takatomo Mihana, Michihiro Koibuchi, Tetsuya Kawanishi, Makoto Naruse
2023	—	`conf`	Performance Improvement of Federated Learning Server using Smart NIC. CANDARW Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani
2022	C	`conf`	A Hardware Trojan Exploiting Coherence Protocol on NoCs. PDCAT Yoshiya Shikama, Michihiro Koibuchi, Hideharu Amano
2022	C	`conf`	A High-Radix Circulant Network Topology for Efficient Collective Communication. PDCAT Ke Cui, Michihiro Koibuchi
2022	Misc	`conf`	A Scalable Distributed Radix Sorter for FPGA Clusters using High-Bandwidth Memory Networks. FCCM Yutaka Urino, Takanori Shimizu, Hiroshi Yamaguchi, Kenji Mizutani, Shigeru Nakamura, Tatsuya Usuki, Michihiro Koibuchi
2022	J	`jnl`	A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2022	J	`jnl`	Accelerating parallel data processing using optically tightly coupled FPGAs. JOCN Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi
2022	J	`jnl`	Boosting the Performance of Interconnection Networks by Selective Data Compression. IEICE Trans. Inf. Syst. Naoya Niwa, Hideharu Amano, Michihiro Koibuchi
2022	—	`conf`	Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2022	—	`conf`	Message from the Organizers: CANDAR 2022. CANDAR Jacir Luiz Bordim, Michihiro Koibuchi, Satoshi Fujita, Koji Nakano
2022	A	`conf`	Scalable Low-Latency Inter-FPGA Networks. IPDPS Kien Trung Pham, Truong Thao Nguyen, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi
2021	C	`conf`	A Case for Low-Latency Network-on-Chip using Compression Routers. PDP Naoya Niwa, Yoshiya Shikama, Hideharu Amano, Michihiro Koibuchi
2021	B	`conf`	Accelerating MPI Communication Using Floating-point Compression on Lossy Interconnection Networks. LCN Yao Hu, Michihiro Koibuchi
2021	—	`conf`	Accelerating Parallel Sort on Tightly-Coupled FPGAs enabled by Onboard Si-Photonics Transceivers. OFC Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi
2021	J	`jnl`	An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2021	—	`conf`	GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2021	J	`jnl`	Improving the Performance of Circuit-Switched Interconnection Network for a Multi-FPGA System. IEICE Trans. Inf. Syst. Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2021	—	`conf`	Low-Latency High-Bandwidth Interconnection Networks by Selective Packet Compression. CANDAR Naoya Niwa, Hideharu Amano, Michihiro Koibuchi
2021	C	`conf`	Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP Yoshiya Shikama, Ryuta Kawano, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi
2021	J	`jnl`	OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives. IEEE Trans. Computers Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi
2021	C	`conf`	Packet Forwarding Cache of Commodity Switches for Parallel Computers. CLUSTER Shoichi Hirasawa, Hayato Yamaki, Michihiro Koibuchi
2021	—	`conf`	The Case for Disjoint Job Mapping on High-Radix Networked Parallel Computers. ICA3PP (2) Yao Hu, Michihiro Koibuchi
2020	—	`conf`	A Diagonal Checksum Algorithm-Based Fault Tolerance for Parallel Matrix Multiplication. CANDAR (Workshops) Ke Cui, Michihiro Koibuchi
2020	J	`jnl`	A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2020	C	`conf`	Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2020	J	`jnl`	Application Mapping and Scheduling of Uncertain Communication Patterns onto Non-Random and Random Network Topologies. IEICE Trans. Inf. Syst. Yao Hu, Michihiro Koibuchi
2020	C	`conf`	Dual-Plane Isomorphic Hypercube Network. HPC Asia Takeo Hosomi, Ryota Yasudo, Michihiro Koibuchi, Shinji Shimojo
2020	J	`jnl`	Efficient Two-Opt Collective-Communication Operations on Low-Latency Random Network Topologies. IEICE Trans. Inf. Syst. Ke Cui, Michihiro Koibuchi
2020	—	`conf`	Implementing a Multi-ejection Switch and Making the Use of Multiple Lanes in a Circuit-switched Multi-FPGA System. CANDAR (Workshops) Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Yao Hu, Michihiro Koibuchi, Hideharu Amano
2020	J	`jnl`	Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2019	—	`conf`	A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System. MCSoC Keita Azegami, Kazusa Musha, Kazuei Hironaka, Akram Ben Ahmed, Michihiro Koibuchi, Yao Hu, Hideharu Amano
2019	J	`jnl`	Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2019	B	`conf`	Diameter/ASPL-Based Mapping of Applications with Uncertain Communication over Random Interconnection Networks. ICPADS Yao Hu, Michihiro Koibuchi
2019	J	`jnl`	Foreword. IEICE Trans. Inf. Syst. Michihiro Koibuchi
2019	—	`conf`	Low-Latency Error-Prone Optical Networks for Fast Approximate Computation on High-End Datacenters. OECC/PSC Michihiro Koibuchi
2019	J	`jnl`	Optimizing Slot Utilization and Network Topology for Communication Pattern on Circuit-Switched Parallel Computing Systems. IEICE Trans. Inf. Syst. Yao Hu, Michihiro Koibuchi
2019	A*	`conf`	Sparse 3-D NoCs with Inductive Coupling. DAC Michihiro Koibuchi, Lambert T. Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova
2019	B	`conf`	The Case for Water-Immersion Computer Boards. ICPP Michihiro Koibuchi, Ikki Fujiwara, Naoya Niwa, Tomohiro Totoki, Shoichi Hirasawa
2019	—	`conf`	The Impact of Application Mapping on Non-Random and Random Network Topologies. ISPA/BDCloud/SocialCom/SustainCom Yao Hu, Michihiro Koibuchi
2018	—	`conf`	Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC Akram Ben Ahmed, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	—	`conf`	An Extension of A Temperature Modeling Tool HotSpot 6.0 for Castle-of-Chips Stacking. CANDAR Workshops Tomohiro Totoki, Michihiro Koibuchi, Hideharu Amano
2018	—	`conf`	An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops Naoya Niwa, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	—	`conf`	AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS Akram Ben Ahmed, Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2018	J	`jnl`	Enhancing Job Scheduling on Inter-Rackscale Datacenters with Free-Space Optical Links. IEICE Trans. Inf. Syst. Yao Hu, Michihiro Koibuchi
2018	B	`conf`	Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. NCA Truong Thao Nguyen, Hiroki Matsutani, Michihiro Koibuchi
2018	—	`conf`	Performance Evaluation of Collective Communication on Random Network Topology. CANDAR Workshops Ke Cui, Michihiro Koibuchi
2018	J	`jnl`	Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2018	—	`conf`	The Impact of Job Mapping on Random Network Topology. CANDAR Workshops Yao Hu, Michihiro Koibuchi
2017	—	`conf`	3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC Hiroshi Nakahara, Ryota Yasudo, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2017	C	`conf`	A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara, Henri Casanova
2017	C	`conf`	A Case of Electrical Circuit Switched Interconnection Network for Parallel Computers. PDCAT Yao Hu, Tomohiro Kudoh, Michihiro Koibuchi
2017	J	`jnl`	A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017	J	`jnl`	A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017	B	`conf`	Cable-geometric error-prone approach for low-latency interconnection networks. CCGrid Thao-Nguyen Nguyen, Michihiro Koibuchi
2017	J	`jnl`	Distributed Shortcut Networks: Low-Latency Low-Degree Non-Random Topologies Targeting the Diameter and Cable Length Trade-Off. IEEE Trans. Parallel Distributed Syst. Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi, Khanh-Van Nguyen
2017	B	`conf`	HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS Ryuta Kawano, Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2017	A*	`conf`	High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA Daichi Fujiki, Kiyo Ishii, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi
2017	B	`conf`	In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani
2017	B	`conf`	Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP Ryota Yasudo, Michihiro Koibuchi, Koji Nakano, Hiroki Matsutani, Hideharu Amano
2017	—	`conf`	SINET5: A low-latency and high-bandwidth backbone network for SDN/NFV Era. ICC Takashi Kurimoto, Shigeo Urushidani, Hiroshi Yamada, Kenjiro Yamanaka, Motonori Nakamura, Shunji Abe, Kensuke Fukuda, Michihiro Koibuchi, Hiroki Takakura, Shigeki Yamada, Yusheng Ji
2017	J	`jnl`	Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2017	—	`conf`	Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC Yao Hu, Hiroaki Hara, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2016	—	`conf`	A diagonal cabling approach to data center and HPC systems. SoICT Truong Thao Nguyen, Ikki Fujiwara, Michihiro Koibuchi
2016	—	`conf`	A fully meshed backbone network for data-intensive sciences and SDN services. ICUFN Takashi Kurimoto, Shigeo Urushidani, Hiroshi Yamada, Kenjiro Yamanaka, Motonori Nakamura, Shunji Abe, Kensuke Fukuda, Michihiro Koibuchi, Yusheng Ji, Hiroki Takakura, Shigeki Yamada
2016	C	`conf`	ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS Ryuta Kawano, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	—	`conf`	An Interconnection Network Exploiting Trade-Off between Routing Table Size and Path Length. CANDAR Thanh-Chung Kieu, Khanh-Van Nguyen, Nguyen T. Truong, Ikki Fujiwara, Michihiro Koibuchi
2016	C	`conf`	Deterministic Construction of Regular Geometric Graphs with Short Average Distance and Limited Edge Length. ICA3PP Satoshi Fujita, Koji Nakano, Michihiro Koibuchi, Ikki Fujiwara
2016	J	`jnl`	Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano
2016	B	`conf`	HPC Job Mapping over Reconfigurable Wireless Links. CCGrid Yao Hu, Ikki Fujiwara, Michihiro Koibuchi
2016	J	`jnl`	Job Mapping and Scheduling on Free-Space Optical Networks. IEICE Trans. Inf. Syst. Yao Hu, Ikki Fujiwara, Michihiro Koibuchi
2016	—	`conf`	LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	J	`jnl`	Layout-Conscious Expandable Topology for Low-Degree Interconnection Networks. IEICE Trans. Inf. Syst. Truong Thao Nguyen, Khanh-Van Nguyen, Ikki Fujiwara, Michihiro Koibuchi
2016	J	`jnl`	Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. Akram Ben Ahmed, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2016	J	`jnl`	Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. IEICE Trans. Inf. Syst. Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	J	`jnl`	Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express Michihiro Koibuchi, Ikki Fujiwara, Kiyo Ishii, Shu Namiki, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh
2016	C	`conf`	Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP Daichi Fujiki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2016	B	`conf`	Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. ICPP Koji Nakano, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara, Michihiro Koibuchi
2016	C	`conf`	Suitability of the Random Topology for HPC Applications. PDP Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi
2016	—	`conf`	Towards Ideal Hop Counts in Interconnection Networks with Arbitrary Size. CANDAR Michihiro Koibuchi, Ikki Fujiwara, Fabien Chaix, Henri Casanova
2015	—	`conf`	A metamorphotic Network-on-Chip for various types of parallel applications. ASAP Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2015	A*	`conf`	Augmenting low-latency HPC network with free-space optical links. HPCA Ikki Fujiwara, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova
2015	—	`conf`	Enabling Ideal Job Mapping on Wireless Supercomputers and Datacenters. CANDAR Yao Hu, Ikki Fujiwara, Michihiro Koibuchi
2015	—	`conf`	Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. MCSoC Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2015	J	`jnl`	New Directions for a Japanese Academic Backbone Network. IEICE Trans. Inf. Syst. Shigeo Urushidani, Shunji Abe, Kenjiro Yamanaka, Kento Aida, Shigetoshi Yokoyama, Hiroshi Yamada, Motonori Nakamura, Kensuke Fukuda, Michihiro Koibuchi, Shigeki Yamada
2015	—	`conf`	On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura
2015	C	`conf`	Optimized Core-Links for Low-Latency NoCs. PDP Ryuta Kawano, Seiichi Tade, Ikki Fujiwara, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2015	—	`conf`	Singularity of Future Computer-System Networks. SoICT Michihiro Koibuchi
2015	J	`jnl`	Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. IEEE Trans. Parallel Distributed Syst. Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
2015	J	`jnl`	The Case for Network Coding for Collective Communication on HPC Interconnection Networks. IEICE Trans. Inf. Syst. Ahmed Shalaby, Ikki Fujiwara, Michihiro Koibuchi
2014	J	`jnl`	3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2014	—	`conf`	Darkfiber Planning for Extensible HPC Network Design under Uncertainties. CANDAR Fabien Chaix, Ikki Fujiwara, Michihiro Koibuchi
2014	J	`jnl`	Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2014	J	`jnl`	Extreme Big Data (EBD): Next Generation Big Data Infrastructure Technologies Towards Yottabyte/Year. Supercomput. Front. Innov. Satoshi Matsuoka, Hitoshi Sato, Osamu Tatebe, Michihiro Koibuchi, Ikki Fujiwara, Shuji Suzuki, Masanori Kakuta, Takashi Ishida, Yutaka Akiyama, Toyotaro Suzumura, Koji Ueno, Hiroki Kanezashi, Takemasa Miyoshi
2014	C	`conf`	Hierarchical Network Coding for Collective Communication on HPC Interconnects. PDP Ahmed Shalaby, Mohamed El-Sayed Ragab, Victor Goulart, Ikki Fujiwara, Michihiro Koibuchi
2014	J	`jnl`	Highly available network design and resource management of SINET4. Telecommun. Syst. Shigeo Urushidani, Michihiro Aoki, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Koibuchi, Yusheng Ji, Shigeki Yamada
2014	B	`conf`	Layout-aware expandable low-degree topology. ICPADS Nguyen T. Truong, Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Fabien Chaix, Michihiro Koibuchi
2014	A	`conf`	Low-latency wireless 3D NoCs via randomized shortcut chips. DATE Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano
2014	A	`conf`	Skywalk: A Topology for HPC Networks with Low-Delay Switches. IPDPS Ikki Fujiwara, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
2013	J	`jnl`	A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation. IEICE Trans. Inf. Syst. Cisse Ahmadou Dit Adi, Michihiro Koibuchi, Masato Yoshimi, Hidetsugu Irie, Tsutomu Yoshinaga
2013	—	`conf`	A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. ICA3PP (2) Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013	—	`conf`	A case for wireless 3D NoCs for CMPs. ASP-DAC Hiroki Matsutani, Paul Bogdan, Radu Marculescu, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2013	B	`conf`	Distributed Shortcut Networks: Layout-Aware Low-Degree Topologies Exploiting Small-World Effect. ICPP Van K. Nguyen, Nhat T. X. Le, Ikki Fujiwara, Michihiro Koibuchi
2013	—	`conf`	Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. COOL Chips Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013	—	`conf`	Future Low-Latency Networks for High Performance Computing. CANDAR Michihiro Koibuchi
2013	—	`conf`	Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. NOCS Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2013	A*	`conf`	Layout-conscious random topologies for HPC off-chip interconnects. HPCA Michihiro Koibuchi, Ikki Fujiwara, Hiroki Matsutani, Henri Casanova
2013	J	`jnl`	Many-cores and On-chip Interconnects (NII Shonan Meeting 2013-8). NII Shonan Meet. Rep. Tomohiro Yoneda, José Flich Cardo, Jiang Xu, Michihiro Koibuchi
2013	B	`conf`	PopCache: Cache more or less based on content popularity for information-centric networking. LCN Kalika Suksomboon, Saran Tarnoi, Yusheng Ji, Michihiro Koibuchi, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Aoki, Shigeo Urushidani, Shigeki Yamada
2012	J	`jnl`	A Survey and Evaluation of Topology-Agnostic Deterministic Routing Algorithms. IEEE Trans. Parallel Distributed Syst. José Flich, Tor Skeie, Andres Mejia, Olav Lysne, Pedro López, Antonio Robles, José Duato, Michihiro Koibuchi, Tomas Rokicki, José Carlos Sancho
2012	A*	`conf`	A case for random shortcut topologies for HPC interconnects. ISCA Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova
2012	—	`conf`	A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2012	C	`conf`	Cabinet Layout Optimization of Supercomputer Topologies for Shorter Cable Length. PDCAT Ikki Fujiwara, Michihiro Koibuchi, Henri Casanova
2012	—	`conf`	Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano
2012	—	`conf`	On incentive-based inter-domain caching for content delivery in future internet architectures. AINTEC Kalika Suksomboon, Yusheng Ji, Michihiro Koibuchi, Kensuke Fukuda, Shunji Abe, Motonori Nakamura, Michihiro Aoki, Shigeo Urushidani, Shigeki Yamada
2012	—	`conf`	Throttling Control for Bufferless Routing in On-chip Networks. MCSoC Yicheng Guan, Cisse Ahmadou Dit Adi, Takefumi Miyoshi, Michihiro Koibuchi, Hidetsugu Irie, Tsutomu Yoshinaga
2011	—	`ch.`	3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011	—	`conf`	A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano
2011	J	`jnl`	A Switch-Tagged Routing Methodology for PC Clusters with VLAN Ethernet. IEEE Trans. Parallel Distributed Syst. Michihiro Koibuchi, Tomohiro Otsuka, Tomohiro Kudoh, Hideharu Amano
2011	—	`conf`	A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano
2011	J	`jnl`	An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2011	J	`jnl`	An analytical network performance model for SIMD processor CSX600 interconnects. J. Syst. Archit. Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano
2011	—	`conf`	Impact of Tohoku earthquake on R&E network in Japan. SWID@CoNEXT Kensuke Fukuda, Michihiro Aoki, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Shigeo Urushidani
2011	Misc	`conf`	Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano
2011	J	`jnl`	Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2011	J	`jnl`	Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2011	—	`ch.`	Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano
2010	—	`conf`	A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS Yuri Nishikawa, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2010	—	`conf`	A Regular Expression Processor Embedded in Service-Friendly Router for Future Internet. ICPP Workshops Yasutsugu Nagatomi, Michihiro Koibuchi, Hideyuki Kawashima, Koichi Inoue, Hiroaki Nishi
2010	—	`conf`	A variable-pipeline on-chip router optimized to traffic pattern. NoCArc@MICRO Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2010	Misc	`conf`	An Efficient Path Setup for a Photonic Network-on-Chip. ICNC Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga
2010	J	`jnl`	Dynamic Resource Allocation and QoS Control Capabilities of the Japanese Academic Backbone Network. Future Internet Shigeo Urushidani, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shunji Abe, Yusheng Ji, Michihiro Aoki, Shigeki Yamada
2010	Misc	`conf`	Hardware Architecture for Supporting High-speed Database Insertion on Service-oriented Router for Future Internet. PDPTA Tomoaki Makino, Koichi Inoue, Michihiro Koibuchi, Hideyuki Kawashima, Hiroaki Nishi
2010	—	`conf`	Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2010	—	`conf`	Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano
2009	J	`jnl`	A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2009	Misc	`conf`	An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano
2009	A	`conf`	An on/off link activation method for low-power ethernet in PC clusters. IPDPS Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano
2009	—	`conf`	Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops José Miguel Montañana Aliaga, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano
2009	J	`jnl`	Design of versatile academic infrastructure for multilayer network services. IEEE J. Sel. Areas Commun. Shigeo Urushidani, Shunji Abe, Yusheng Ji, Kensuke Fukuda, Michihiro Koibuchi, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto
2009	C	`conf`	Efficient Scheduling Algorithms on Bandwidth Reservation Service of Internet Using Metaheuristics. ISDA Tomoyuki Hiroyasu, Kozo Kawasaki, Michihiro Koibuchi, Shigeo Urushidani, Mitsunori Miki, Masato Yoshimi
2009	J	`jnl`	Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano
2009	J	`jnl`	Impact of QoS operations on an experimental testbed network. Simul. Model. Pract. Theory Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji, Kensuke Fukuda, Shunji Abe, Jun Matsukata, Shigeo Urushidani, Shigeki Yamada
2009	—	`conf`	Implementation and Evaluation of Layer-1 Bandwidth-on-Demand Capabilities in SINET3. ICC Shigeo Urushidani, Kensuke Fukuda, Yusheng Ji, Michihiro Koibuchi, Shunji Abe, Motonori Nakamura, Shigeki Yamada, Kaori Shimizu, Rie Hayashi, Ichiro Inoue, Kohei Shiomoto
2009	C	`conf`	Performance Analysis of ClearSpeed's CSX600 Interconnects. ISPA Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Akihiro Shitara, Kenichi Miura, Hideharu Amano
2009	A*	`conf`	Prediction router: Yet another low latency on-chip router architecture. HPCA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga
2008	—	`conf`	A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston
2008	B	`conf`	A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi
2008	—	`conf`	Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano
2008	C	`conf`	Impact of topology and link aggregation on a PC cluster with Ethernet. CLUSTER Takafumi Watanabe, Masahiro Nakao, Tomoyuki Hiroyasu, Tomohiro Otsuka, Michihiro Koibuchi
2008	—	`conf`	Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang
2008	—	`conf`	Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano
2007	J	`jnl`	A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007	B	`conf`	A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007	J	`jnl`	An Effective Design of Deadlock-Free Routing Algorithms Based on 2D Turn Model for Irregular Networks. IEEE Trans. Parallel Distributed Syst. Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano
2007	J	`jnl`	Architectural Design of Next-Generation Science Information Network. IEICE Trans. Commun. Shigeo Urushidani, Shunji Abe, Kensuke Fukuda, Jun Matsukata, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada
2007	B	`conf`	Investigating QoS Performance on a Testbed Network. ICCCN Jumpot Phuritatkul, Kien Nguyen, Michihiro Koibuchi, Yusheng Ji
2007	B	`conf`	Layer-1 Bandwidth on Demand Services in SINET3. GLOBECOM Shigeo Urushidani, Jun Matsukata, Kensuke Fukuda, Shunji Abe, Yusheng Ji, Michihiro Koibuchi, Shigeki Yamada, Kaori Shimizu, Tomonori Takeda, Ichiro Inoue, Kohei Shiomoto
2007	B	`conf`	Performance Improvement Methodology for ClearSpeed's CSX600. ICPP Yuri Nishikawa, Michihiro Koibuchi, Masato Yoshimi, Kenichi Miura, Hideharu Amano
2007	A	`conf`	Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2007	B	`conf`	Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006	—	`conf`	A Parametric Study of Scalable Interconnects on FPGAs. ERSA Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano
2006	J	`jnl`	A Simple Data Transfer Technique Using Local Address for Networks-on-Chips. IEEE Trans. Parallel Distributed Syst. Michihiro Koibuchi, Kenichiro Anjo, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
2006	—	`conf`	A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. PDCS Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006	C	`conf`	Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2006	B	`conf`	Switch-tagged VLAN Routing Methodology for PC Clusters with Ethernet. ICPP Tomohiro Otsuka, Michihiro Koibuchi, Tomohiro Kudoh, Hideharu Amano
2005	Misc	`conf`	Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano
2005	J	`jnl`	Enforcing in-order packet delivery in system area networks with adaptive routing. J. Parallel Distributed Comput. Michihiro Koibuchi, Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato
2005	A	`conf`	In-Order Packet Delivery in Interconnection Networks using Adaptive Routing. IPDPS Juan Carlos Martínez, José Flich, Antonio Robles, Pedro López, José Duato, Michihiro Koibuchi
2005	J	`jnl`	MMLRU Selection Function: A Simple and Efficient Output Selection Function in Adaptive Routing. IEICE Trans. Inf. Syst. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2005	—	`conf`	Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano
2005	J	`jnl`	Path selection algorithm: the strategy for designing deterministic routing from alternative paths. Parallel Comput. Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2005	J	`jnl`	Performance Evaluation of Deterministic Routings, Multicasts, and Topologies on RHiNET-2 Cluster. IEEE Trans. Parallel Distributed Syst. Michihiro Koibuchi, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano
2005	B	`conf`	VLAN-Based Minimal Paths in PC Cluster with Ethernet on Mesh and Torus. ICPP Tomohiro Otsuka, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2004	A	`conf`	BLACK-BUS: A New Data-Transfer Technique Using Local Address on Networks-on-Chips. IPDPS Kenichiro Anjo, Yutaka Yamada, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2004	C	`conf`	Folded Fat H-Tree: An Interconnection Topology for Dynamically Reconfigurable Processor Array. EUC Yutaka Yamada, Hideharu Amano, Michihiro Koibuchi, Akiya Jouraku, Kenichiro Anjo, Katsunobu Nishimura
2003	B	`conf`	Descending Layers Routing: A Deadlock-Free Deterministic Routing using Virtual Channels in System Area Networks with Irregular Topologies. ICPP Michihiro Koibuchi, Akiya Jouraku, Konosuke Watanabe, Hideharu Amano
2003	C	`conf`	Performance Evaluation of Routing Algorithms in RHiNET-2 Cluster. CLUSTER Michihiro Koibuchi, Konosuke Watanabe, Kenichi Kono, Akiya Jouraku, Hideharu Amano
2002	—	`conf`	Routing Algorithms Based on 2D Turn Model for Irregular Networks. ISPAN Akiya Jouraku, Michihiro Koibuchi, Hideharu Amano, Akira Funahashi
2002	Misc	`conf`	The Impact of Path Selection Algorithm of Adaptive Routing for Implementing Deterministic Routing. PDPTA Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano
2001	B	`conf`	L-Turn Routing: An Adaptive Routing in Irregular Networks. ICPP Michihiro Koibuchi, Akira Funahashi, Akiya Jouraku, Hideharu Amano
2001	—	`conf`	MMLRU Selection Function: An Output Selection Function on Adaptive Routing. PDCS Michihiro Koibuchi, Akiya Jouraku, Akira Funahashi, Hideharu Amano
2001	Misc	`conf`	The impact of output selection function on adaptive routing. CATA Akira Funahashi, Michihiro Koibuchi, Akiya Jouraku, Hideharu Amano