Michiaki Muraoka

19 papers A* 3Misc 1Journal 1Unranked 14
YearRankTypeTitle / Venue / Authors
2014 — conf
A critical net reshape-router for high-performance VLSI layout design.
APCCAS
Yusuke Morimoto, Mitsuru Matsushita, Michiaki Muraoka, Masahiko Toyonaga
2013 — conf
A multilayer crosstalk avoidance router using restricted maze grids.
MWSCAS
Yoshiya Fujii, Michiaki Muraoka, Masahiko Toyonaga
2004 J jnl
A DFT Selection Method for Reducing Test Application Time of System-on-Chips.
IEICE Trans. Inf. Syst.
Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
2004 — conf
Design methodology for SoC arthitectures based on reusable virtual cores.
ASP-DAC
Michiaki Muraoka, Hiroaki Nishi, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada
2003 — conf
A DFT Selection Method for Reducing Test Application Time of System-on-Chips.
Asian Test Symposium
Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara
2003 — conf
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.
Asian Test Symposium
Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara
2003 — conf
Synthesis for SoC architecture using VCores.
ASP-DAC
Hiroaki Nishi, Michiaki Muraoka, Rafael K. Morizawa, Hideaki Yokota, Hideyuki Hamada
2003 — conf
VCDS tool demonstration.
ASP-DAC
Rafael K. Morizawa, Kazuo Tanaka, Keisuke Watanabe, Yuji Kaitsu, Shoji Hanamura, Takao Shinsha, Michiaki Muraoka
2003 — conf
VCore-based design methodology.
ASP-DAC
Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida
2003 — conf
VCore-based platform for SoC design.
ASP-DAC
Yoichi Onishi, Michiaki Muraoka, Makoto Utsuki, Naoyuki Tsubaki
2002 — conf
A SoC Test Strategy Based on a Non-Scan DFT Method.
Asian Test Symposium
Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka
2002 — conf
A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique.
Asian Test Symposium
Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
2002 Misc conf
A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits.
VTS
Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka
1997 — conf
A Partial Scan Design Method Based on n-Fold Line-up Structures.
Asian Test Symposium
Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu
1996 — conf
A Design for testability Method Using RTL Partitioning.
Asian Test Symposium
Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka
1995 — conf
Design for testability using register-transfer level partial scan selection.
ASP-DAC
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka
1993 A* conf
A State Traversal Algorithm Using a State Covariance Matrix.
DAC
Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin
1985 A* conf
ACTAS: an accurate timing analysis system for VLSI.
DAC
Michiaki Muraoka, Hirokazu Iida, Hideyuki Kikuchihara, Michio Murakami, Kazuyuki Hirakawa
1982 A* conf
Logic simulation for LSI.
DAC
Kazuyuki Hirakawa, Noboru Shiraki, Michiaki Muraoka