Michele Portolan

47 papers A 12B 10C 8Misc 5Journal 6Unranked 6

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Enhanced BIST Architecture for Analog and Mixed-Signal Systems with On-Chip APRMLS and Machine Learning Analysis. ICCAD Jules Kouamo, Emmanuel Simeu, Michele Portolan
2025	C	`conf`	Machine Learning-Based Parametric Fault Detection in Analog and Mixed-Signal Circuits. IOLTS Jules Kouamo, Emmanuel Simeu, Michele Portolan
2024	J	`jnl`	True Interactive Testing Based on IJTAG. IEEE Des. Test Michele Portolan
2024	B	`conf`	What Would Interactive Testing With 1687 Look Like? ETS Michele Portolan, Martin Keim, J. F. Coté, Hans-Martin Von Staud
2023	—	`conf`	Evaluating the Impact of Aging on Path-Delay Self-Test Libraries. DFT Riccardo Cantoro, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
2023	Misc	`conf`	Refreshing the JTAG Family. VTS Michele Portolan, Martin Keim, Jeff Rearick, Heiko Ehrenberg
2023	J	`jnl`	Self-Test Library Generation for In-Field Test of Path Delay Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Lorena Anghel, Riccardo Cantoro, Riccardo Masante, Michele Portolan, Sandro Sartoni, Matteo Sonza Reorda
2022	A	`conf`	Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure. ITC Michele Portolan, Antonios Pavlidis, Giorgio Di Natale, Eric Faehn, Haralampos-G. Stratigopoulos
2022	J	`jnl`	Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions. IEEE Des. Test Michele Portolan, Emanuele Valea, Paolo Maistri, Giorgio Di Natale
2022	A	`conf`	IEEE P1687.1: Extending the Network Boundaries for Test. ITC Michael Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Songlin Zuo
2021	B	`conf`	Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling of Non-TAP Interfaces. ETS Hans Martin von Staudt, Bradford G. Van Treuren, Jeff Rearick, Michele Portolan, Martin Keim
2021	—	`conf`	Secure Test with RSNs: Seamless Authenticated Extended Confidentiality. NEWCAS Paolo Maistri, Vincent Reynaud, Michele Portolan, Régis Leveugle
2021	A	`conf`	Security EDA Extension through P1687.1 and 1687 Callbacks. ITC Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle, Giorgio Di Natale
2020	C	`conf`	A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System. IOLTS Michele Portolan, R. Silveira Feitoza, Ghislain Takam Tchendjou, Vincent Reynaud, Kalpana Senthamarai Kannan, Manuel J. Barragán, Emmanuel Simeu, Paolo Maistri, Lorena Anghel, Régis Leveugle, Salvador Mir
2020	J	`jnl`	Automated Testing Flow: The Present and the Future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michele Portolan
2020	B	`conf`	Dynamic Authentication-Based Secure Access to Test Infrastructure. ETS Michele Portolan, Vincent Reynaud, Paolo Maistri, Régis Leveugle
2020	B	`conf`	Linking Chip, Board, and System Test via Standards. ETS Michele Portolan, Jeff Rearick, Martin Keim
2020	A	`conf`	Modeling Novel Non-JTAG IEEE 1687-Like Architectures. ITC Mike Laisne, Alfred L. Crouch, Michele Portolan, Martin Keim, Hans Martin von Staudt, M. Abdalwahab, Bradford G. Van Treuren, Jeff Rearick
2020	A	`conf`	New Perspectives on Core In-field Path Delay Test. ITC Riccardo Cantoro, Dario Foti, Sandro Sartoni, Matteo Sonza Reorda, Lorena Anghel, Michele Portolan
2019	B	`conf`	A Functional Approach to Test and Debug of IEEE 1687 Reconfigurable Networks. ETS Michele Portolan, Riccardo Cantoro, Ernesto Sánchez
2019	B	`conf`	Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale
2019	B	`conf`	Approximate computing design exploration through data lifetime metrics. ETS Alessandro Savino, Michele Portolan, Régis Leveugle, Stefano Di Carlo
2019	A	`conf`	Simulation-based Equivalence Checking between IEEE 1687 ICL and RTL. ITC Aleksa Damljanovic, Artur Jutman, Michele Portolan, Ernesto Sánchez, Giovanni Squillero, Anton Tsertov
2017	B	`conf`	Mixed-signal BIST computation offloading using IEEE 1687. ETS Michele Portolan, Manuel J. Barragán, Rshdee Alhakim, Salvador Mir
2017	C	`conf`	Reliability of computing systems: From flip flops to variables. IOLTS Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle
2016	B	`conf`	A novel test generation and application flow for functional access to IEEE 1687 instruments. ETS Michele Portolan
2016	A	`conf`	Accessing 1687 systems using arbitrary protocols. ITC Michele Portolan
2016	C	`conf`	Evaluating application-aware soft error effects in digital circuits without fault injections or probabilistic computations. IOLTS K. Chibani, Michele Portolan, Régis Leveugle
2016	—	`conf`	Student-driven development of a digital tester. EWME Michele Portolan, Robin Rolland
2015	Misc	`conf`	Special session 8C: E.J. McCluskey doctoral thesis award semi-final. VTS Michele Portolan, K. Huang
2014	—	`conf`	Criticality evaluation of embedded software running on a pipelined microprocessor and impact of compilation options. ICECS K. Chibani, Salma Bergaoui, Michele Portolan, Régis Leveugle
2014	C	`conf`	Fast accurate evaluation of register lifetime and criticality in a pipelined microprocessor. VLSI-SoC K. Chibani, Mohamed Ben Jrad, Michele Portolan, Régis Leveugle
2014	Misc	`conf`	Special session 8A: E.J. McCluskey Doctoral Thesis Award semi-final. VTS Michele Portolan, Michail Maniatakos
2013	B	`conf`	Automatic equivalent model generation and evolution for small cell networks. WiOpt Davide Cherubini, Michele Portolan
2013	J	`jnl`	Executing IJTAG: Are Vectors Enough? IEEE Des. Test Michele Portolan, Bradford G. Van Treuren, Suresh Goyal
2013	Misc	`conf`	Special session 3B: E.J. McCluskey Doctoral Thesis Award semi-final - Posters. VTS Michele Portolan, Michail Maniatakos
2013	Misc	`conf`	Special session 8A: E.J. McCluskey doctoral thesis award semi-final - presentations. VTS Michele Portolan, Michail Maniatakos
2012	A	`conf`	Packet-based JTAG for remote testing. ITC Michele Portolan
2010	J	`jnl`	A Common Language Framework for Next-Generation Embedded Testing. IEEE Des. Test Comput. Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2010	A	`conf`	Scan chain securization though Open-Circuit Deadlocks. ITC Michele Portolan, Bradford G. Van Treuren, Suresh Goyal
2009	A	`conf`	Scalable and efficient integrated test architecture. ITC Michele Portolan, Suresh Goyal, Bradford G. Van Treuren
2008	A	`conf`	A New Language Approach for IJTAG. ITC Michele Portolan, Suresh Goyal, Bradford G. Van Treuren, Chen-Huan Chiang, Tapan J. Chakraborty, Thomas B. Cook
2008	—	`conf`	Usefulness and effectiveness of HW and SW protection mechanisms in a processor-based system. ICECS Pierre Vanhauwaert, Michele Portolan, Régis Leveugle, Philippe Roche
2007	—	`conf`	Effective Checkpoint and Rollback Using Hardware/OS Collaboration. DFT Michele Portolan, Régis Leveugle
2005	C	`conf`	On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors. IOLTS Michele Portolan, Régis Leveugle
2005	C	`conf`	Towards a Secure and Reliable System. EUC Michele Portolan, Régis Leveugle
2004	C	`conf`	Operating System Function Reuse to Achieve Low-Cost Fault Tolerance. IOLTS Michele Portolan, Régis Leveugle