Michel Renovell

188 papers A 19B 15C 9Misc 21Journal 58Unranked 65

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Novel Defect Model Induced by a Single Dust Particle Contamination in the FinFET Gate Fingers. J. Electron. Test. Gustavo Aguirre, Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli
2025	J	`jnl`	Cost-Effective Analytical Models of Resistive Opens Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Gustavo Aguirre, Freddy Forero, Víctor H. Champac, Michel Renovell, Florence Azaïs, Mariane Comte, Jean-Marc Gallière
2023	—	`conf`	A New Defect Model due to a Dust Particle Affecting the Fingers of FinFET Logic Gates. LATS Víctor H. Champac, Freddy Forero, Michel Renovell, Leonardo Miceli
2023	J	`jnl`	B-open Defect: A Novel Defect Model in FinFET Technology. ACM J. Emerg. Technol. Comput. Syst. Freddy Forero, Víctor H. Champac, Michel Renovell
2019	—	`conf`	A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells. LATS Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac
2019	J	`jnl`	Analytical Models for the Evaluation of Resistive Short Defect Detectability in Presence of Process Variations: Application to 28nm Bulk and FDSOI Technologies. J. Electron. Test. Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell
2019	B	`conf`	B-open: A New Defect in Nanometer Technologies due to SADP Process. ETS Freddy Forero, Michel Renovell, Víctor H. Champac
2019	J	`jnl`	Modeling and Detectability of Full Open Gate Defects in FinFET Technology. IEEE Trans. Very Large Scale Integr. Syst. Freddy Forero, Hector Villacorta, Michel Renovell, Víctor H. Champac
2018	J	`jnl`	Detectability Challenges of Bridge Defects in FinFET Based Logic Cells. J. Electron. Test. Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac
2018	—	`conf`	Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell
2017	—	`conf`	Analysis of short defects in FinFET based logic cells. LATS Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac
2017	—	`conf`	Comprehensive Study for Detection of Weak Resistive Open and Short Defects in FDSOI Technology. ISVLSI Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh
2017	B	`conf`	Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. ETS Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell, Keshav Singh
2017	B	`conf`	Mitigating read & write errors in STT-MRAM memories under DVS. ETS Elena-Ioana Vatajelu, Rosa Rodríguez-Montañés, Michel Renovell, Joan Figueras
2017	J	`jnl`	Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies. J. Electron. Test. Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell
2017	—	`conf`	Spot defect modeling: Past and evolution. DTIS Michel Renovell
2016	B	`conf`	Behavior and test of open-gate defects in FinFET based cells. ETS Francisco Mesalles, Hector Villacorta, Michel Renovell, Víctor H. Champac
2016	—	`conf`	Comparative study of Bulk, FDSOI and FinFET technologies in presence of a resistive short defect. LATS Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell
2016	J	`jnl`	Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations. IEEE Trans. Very Large Scale Integr. Syst. Jesús Moreno, Michel Renovell, Víctor H. Champac
2016	—	`conf`	Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI - LVT and RVT Configurations. ISVLSI Amit Karel, Mariane Comte, Jean-Marc Gallière, Florence Azaïs, Michel Renovell
2015	—	`conf`	A Framework for Efficient Implementation of Analog/RF Alternate Test with Model Redundancy. ISVLSI Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
2015	J	`jnl`	Efficiency evaluation of analog/RF alternate test: Comparative study of indirect measurement selection strategies. Microelectron. J. Syhem Larguech, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
2015	B	`conf`	Power-aware voltage tuning for STT-MRAM reliability. ETS Elena I. Vatajelu, Rosa Rodríguez-Montañés, Stefano Di Carlo, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015	A	`conf`	Read/write robustness estimation metrics for spin transfer torque (STT) MRAM cell. DATE Elena I. Vatajelu, Rosa Rodríguez-Montañés, Marco Indaco, Michel Renovell, Paolo Prinetto, Joan Figueras
2015	—	`conf`	Toward Adaptation of ADCs to Operating Conditions through On-chip Correction. ISVLSI Vincent Kerzerho, Ludovic Guillaume-Sage, Florence Azaïs, Mariane Comte, Michel Renovell, Serge Bernard
2014	—	`conf`	DTIS 2014 foreword. DTIS Ioannis Voyiatzis, Michel Renovell, Mohamed Masmoudi, Paolo Prinetto, Giorgio Di Natale
2014	J	`jnl`	Editorial. Microelectron. J. Serge Bernard, Patrick Garda, Michel Renovell
2014	J	`jnl`	Enhancing confidence in indirect analog/RF testing against the lack of correlation between regular parameters and indirect measurements. Microelectron. J. Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
2014	—	`conf`	Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing. LATW Syhem Larguech, Florence Azaïs, Serge Bernard, Vincent Kerzerho, Mariane Comte, Michel Renovell
2014	A	`conf`	New implementions of predictive alternate analog/RF test with augmented model redundancy. DATE Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Michel Renovell
2014	C	`conf`	Solutions for the self-adaptation of communicating systems in operation. IOLTS Martin Andraud, Anthony Deluthault, Mouhamadou Dieng, Florence Azaïs, Serge Bernard, Philippe Cauvet, Mariane Comte, Thibault Kervaon, Vincent Kerzerho, Salvador Mir, Paul-Henri Pugliesi-Conti, Michel Renovell, Fabien Soulier, Emmanuel Simeu, Haralampos-G. D. Stratigopoulos
2014	J	`jnl`	Sram cell stability metric under transient voltage noise. Microelectron. J. Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
2014	J	`jnl`	Testing for gate oxide short defects using the detectability interval paradigm. it Inf. Technol. Jean-Marc Gallière, Florence Azaïs, Mariane Comte, Michel Renovell
2013	J	`jnl`	A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC. Microelectron. J. Vincent Kerzerho, Serge Bernard, Florence Azaïs, Mariane Comte, Olivier Potin, Chuan Shan, G. Bontorin, Michel Renovell
2013	—	`conf`	Accurate and efficient analytical electrical model of antenna for NFC applications. NEWCAS Mouhamadou Dieng, Mariane Comte, Serge Bernard, Vincent Kerzerho, Florence Azaïs, Michel Renovell, Thibault Kervaon, Paul-Henri Pugliesi-Conti
2013	B	`conf`	Implementing model redundancy in predictive alternate test to improve test confidence. ETS Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell
2013	—	`conf`	MIRID: Mixed-Mode IR-Drop Induced Delay Simulator. Asian Test Symposium Jie Jiang, Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Ilia Polian
2013	—	`conf`	Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays. LATW Marina Aparicio, Mariane Comte, Florence Azaïs, Michel Renovell, Jie Jiang, Ilia Polian, Bernd Becker
2012	—	`conf`	Low voltage testing for interconnect opens under process variations. LATW Jesús Moreno, Víctor H. Champac, Michel Renovell
2012	A	`conf`	Making predictive analog/RF alternate test strategy independent of training set size. ITC Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell
2012	Misc	`conf`	Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma
2011	Misc	`conf`	A new methodology for realistic open defect detection probability evaluation under process variations. VTS Jesús Moreno, Víctor H. Champac, Michel Renovell
2011	J	`jnl`	Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. J. Electron. Test. Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, Michel Renovell
2011	C	`conf`	Influence of parasitic memory effect on single-cell faults in SRAMs. DDECS Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell
2011	—	`conf`	Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium Elena I. Vatajelu, Álvaro Gómez-Pau, Michel Renovell, Joan Figueras
2010	J	`jnl`	Editorial. Microelectron. J. Mohamed Masmoudi, Michel Renovell
2010	—	`conf`	Parasitic memory effect in CMOS SRAMs. IDT Sandra Irobi, Zaid Al-Ars, Michel Renovell
2009	—	`conf`	A multi-converter DFT technique for complex SIP: Concepts and validation. ECCTD Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
2009	Misc	`conf`	An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker
2009	C	`conf`	An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS Florence Azaïs, Yves Bertrand, Michel Renovell
2009	J	`jnl`	Functional Testing of Processor Cores in FPGA-Based Applications. Comput. Informatics Mariusz Wegrzyn, Franc Novak, Anton Biasizzo, Michel Renovell
2009	J	`jnl`	SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian
2008	B	`conf`	A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. ETS Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker
2008	J	`jnl`	ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. VLSI Design Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, Mariane Comte, Omar Chakib
2008	J	`jnl`	On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker
2008	C	`conf`	On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell
2008	C	`ed.`	Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008 DDECS Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová
2008	—	`ed.`	Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008 SBCCI Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta
2007	B	`conf`	"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
2007	J	`jnl`	Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. J. Electron. Test. Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
2007	J	`jnl`	Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. IET Comput. Digit. Tech. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
2007	—	`conf`	Impact of Simultaneous Switching Noise on the Static behavior of Digital CMOS Circuits. ATS Florence Azaïs, Laurent Larguier, Michel Renovell
2007	—	`conf`	SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges. ATS Piet Engelke, Bettina Braitling, Ilia Polian, Michel Renovell, Bernd Becker
2007	—	`conf`	Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. ISVLSI Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell
2007	B	`conf`	System-in-Package, a Combination of Challenges and Solutions. ETS Philippe Cauvet, Serge Bernard, Michel Renovell
2006	B	`conf`	"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. ETS Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
2006	J	`jnl`	A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Des. Test Comput. Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell
2006	—	`conf`	A Specific ATPG technique for Resistive Open with Sequence Recursive Dependency. ATS Michel Renovell, Mariane Comte, Ilia Polian, Piet Engelke, Bernd Becker
2006	J	`jnl`	An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electron. Test. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2006	J	`jnl`	Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electron. Test. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2006	—	`conf`	Delta-IDDQ Testing of Resistive Short Defects. ATS Piet Engelke, Ilia Polian, Hans Manhaeve, Michel Renovell, Bernd Becker
2006	—	`conf`	Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell
2006	Misc	`conf`	Functional Test of Field Programmable Analog Arrays. VTS Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell
2006	J	`jnl`	Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2005	J	`jnl`	A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electron. Test. Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell
2005	J	`jnl`	Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electron. Test. Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
2005	J	`jnl`	Built-in self-test of global interconnects of field programmable analog arrays. Microelectron. J. Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
2005	J	`jnl`	Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electron. Test. Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2005	J	`jnl`	Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand
2005	J	`jnl`	Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
2005	J	`jnl`	Guest Editorial. J. Electron. Test. Adoración Rueda, Michel Renovell, José Luis Huertas
2005	J	`jnl`	Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electron. Test. Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
2005	Misc	`conf`	Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS Ilia Polian, Sandip Kundu, Jean-Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker
2005	Misc	`conf`	Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell
2004	Misc	`conf`	A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure
2004	J	`jnl`	A New FPGA for DSP Applications Integrating BIST Capabilities. J. Electron. Test. Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell
2004	Misc	`conf`	An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell
2004	—	`conf`	Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs
2004	B	`conf`	Automatic test pattern generation for resistive bridging faults. ETS Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2004	C	`conf`	BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	J	`jnl`	Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
2004	J	`jnl`	Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electron. Test. Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
2004	—	`conf`	High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	B	`conf`	Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. ETS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2004	C	`conf`	Scan Design and Secure Chip. IOLTS David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell
2004	A	`conf`	Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski
2004	Misc	`conf`	The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker
2003	A	`conf`	A New Methodology For ADC Test Flow Optimization. ITC Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell
2003	J	`jnl`	A-to-D converters static error detection from dynamic parameter measurement. Microelectron. J. Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell
2003	J	`jnl`	An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Des. Test Comput. Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
2003	C	`conf`	Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2003	—	`conf`	Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2003	J	`jnl`	Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Des. Test Comput. Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell
2003	—	`conf`	Modeling feedback bridging faults with non-zero resistance. ETW Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker
2003	J	`jnl`	Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electron. Test. Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2003	J	`jnl`	On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electron. Test. Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2003	—	`conf`	Requirements for delay testing of look-up tables in SRAM-based FPGAs. ETW Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell
2003	A	`conf`	Simulating Resistive Bridging and Stuck-At Faults. ITC Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker
2003	J	`jnl`	Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. J. Circuits Syst. Comput. Michel Renovell
2002	—	`conf`	A New FPGA for DSP Applications Integrating BIST Capabilities. LATW Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell
2002	—	`conf`	A Structural Test Methodology for SRAM-Based FPGAs. SBCCI Michel Renovell
2002	—	`conf`	A high accuracy triangle-wave signal generator for on-chip ADC testing. ETW Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2002	—	`conf`	Estimating Static Parameters of A-to-D Converters from Spectral Analysis. LATW Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell, Marcelo Lubaszewski
2002	B	`ed.`	Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings FPL Manfred Glesner, Peter Zipf, Michel Renovell
2002	J	`jnl`	Improving Defect Detection in Static-Voltage Testing. IEEE Des. Test Comput. Michel Renovell, Florence Azaïs, Yves Bertrand
2002	—	`conf`	Modeling gate oxide short defects in CMOS minimum transistors. ETW Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2002	—	`conf`	Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian
2001	J	`jnl`	A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2001	Misc	`conf`	A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
2001	J	`jnl`	A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	—	`conf`	Analog BIST Generator for ADC Testing. DFT Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2001	A	`conf`	Boolean and current detection of MOS transistor with gate oxide short. ITC Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand
2001	—	`conf`	Electrical Analysis of Gate Oxide Short in MOS Technologies. LATW Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand
2001	J	`jnl`	Guest Editorial. J. Electron. Test. Michel Renovell
2001	A	`conf`	IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC Michel Renovell, Penelope Faure, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2001	A	`conf`	Implementation of a linear histogram BIST for ADCs. DATE Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	J	`jnl`	On the detectability of CMOS floating gate transistor faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand
2001	—	`conf`	On-Chip Generation of High-Quality Ramp Stimulus With Minimal Silicon Area. LATW Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell
2001	C	`conf`	On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	J	`jnl`	Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electron. Test. Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell
2001	—	`conf`	Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. ISQED Michel Renovell
2000	B	`conf`	A Specific Test Methodology for Symmetric SRAM-Based FPGAs. FPL Michel Renovell
2000	J	`jnl`	An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	—	`conf`	Analyzing the test generation problem for an application-oriented test of FPGAs. ETW Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	J	`jnl`	Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electron. Test. Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand
2000	A	`conf`	Different experiments in test generation for XILINX FPGAs. ITC Michel Renovell, Yervant Zorian
2000	Misc	`conf`	Hardware Resource Minimization for Histogram-Based ADC BIST. VTS Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand
2000	—	`conf`	Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital Converters. LATW Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell
2000	—	`conf`	On the Temperature Dependencies of Analog BIST. LATW Luigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs
2000	A	`conf`	Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
2000	—	`conf`	Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational Circuits. SBCCI Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell
2000	—	`conf`	TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian
2000	—	`conf`	Test Configuration Generation for FPGA Logic Cells. LATW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	J	`jnl`	Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
2000	—	`conf`	Towards an ADC BIST scheme using the histogram test technique. ETW Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell
1999	J	`jnl`	Detection of Defects Using Fault Model Oriented Test Sequences. J. Electron. Test. Michel Renovell, Florence Azaïs, Yves Bertrand
1999	—	`conf`	Functional and structural testing of switched-current circuits. ETW Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand
1999	—	`conf`	Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	A	`conf`	Optimal conditions for Boolean and current detection of floating gate faults. ITC Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq
1999	J	`jnl`	SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electron. Test. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	—	`conf`	Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study. ETW Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1999	A	`conf`	Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	—	`conf`	A Built-In Multi-Mode Stimuli Generator for Analogue and Mixed-Signal Testing. SBCCI Marcelo Lubaszewski, Michel Renovell, Salvador Mir, Florence Azaïs, Yves Bertrand
1998	—	`conf`	A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand
1998	—	`conf`	BISTing Switched-Current Circuits. Asian Test Symposium Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand
1998	Misc	`conf`	Design-For-Testability for Switched-Current Circuits. VTS Florence Azaïs, Michel Renovell, Yves Bertrand, J.-C. Bodin
1998	—	`conf`	From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell
1998	—	`conf`	Microsystems Testing: A Challenge. Asian Test Symposium Michel Renovell
1998	A	`conf`	Novel Technique for Testing FPGAs. DATE Cecilia Metra, Michel Renovell, Giovanni A. Mojoli, Jean-Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi
1998	A	`conf`	Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE Michel Renovell, Florence Azaïs, Yves Bertrand
1998	A	`conf`	RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	—	`conf`	SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	B	`conf`	SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	A	`conf`	SRAM-based FPGA's: testing the LUT/RAM modules. ITC Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1998	—	`conf`	SRAM-based FPGAs: A Structural Test Approach. SBCCI Michel Renovell
1998	—	`conf`	Testing for Floating Gates Defects in CMOS Circuits. Asian Test Symposium Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell
1998	J	`jnl`	Testing the Interconnect of RAM-Based FPGAs. IEEE Des. Test Comput. Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	—	`conf`	On-chip analog output response compaction. ED&TC Michel Renovell, Florence Azaïs, Yves Bertrand
1997	—	`conf`	Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian
1997	A	`conf`	Test Strategy Sensitivity to Defect Parameters. ITC Michel Renovell, Yves Bertrand
1997	Misc	`conf`	Test of RAM-based FPGA: methodology and application to the interconnect. VTS Michel Renovell, Joan Figueras, Yervant Zorian
1996	Misc	`conf`	Bridging fault coverage improvement by power supply control. VTS Michel Renovell, P. Huc, Yves Bertrand
1996	Misc	`conf`	The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC Michel Renovell, P. Huc, Yves Bertrand
1996	Misc	`conf`	The multi-configuration: A DFT technique for analog circuits. VTS Michel Renovell, Florence Azaïs, Yves Bertrand
1995	—	`conf`	A design-for-test technique for multistage analog circuits. Asian Test Symposium Michel Renovell, Florence Azaïs, Yves Bertrand
1995	J	`jnl`	Current testing in dynamic CMOS circuits. J. Electron. Test. Joan Figueras, Michel Renovell
1995	—	`conf`	Serial transistor network modeling for bridging fault simulation. Asian Test Symposium Michel Renovell, P. Huc, Yves Bertrand
1995	—	`conf`	Test configurations to enhance the testability of sequential circuits. Asian Test Symposium S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault
1995	Misc	`conf`	The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS Michel Renovell, P. Huc, Yves Bertrand
1994	Misc	`conf`	CMOS bridging fault modeling. VTS Michel Renovell, P. Huc, Yves Bertrand
1994	Misc	`conf`	The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC Michel Renovell, P. Huc, Yves Bertrand
1993	Misc	`conf`	A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design Yves Bertrand, Frédéric Bancel, Michel Renovell
1993	—	`conf`	Current Testing Viability in Dynamic CMOS Circuits. DFT Michel Renovell, Joan Figueras
1993	A	`conf`	Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC Yves Bertrand, Frédéric Bancel, Michel Renovell
1992	Misc	`conf`	A Low Overhead and High Coverage BIST Scheme for Dynamic CMOS PLAs. VLSI Design Michel Renovell, M. Ildevert, Yves Bertrand
1992	J	`jnl`	Electrical analysis and modeling of floating-gate fault. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michel Renovell, Gaston Cambon
1985	J	`jnl`	FSPICE: a tool for fault modelling in MOS circuits. Integr. Michel Renovell, Gaston Cambon, Daniel Auvergne