Michel R. C. M. Berkelaar

15 papers A 8C 2Journal 2Unranked 3
YearRankTypeTitle / Venue / Authors
2004 C conf
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
ICCD
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
2004 — conf
Layout Driven Optimization of Datapath Circuits using Arithmetic Reasoning.
MBMV
Ingmar Neumann, Dominik Stoffel, Kolja Sulimma, Michel R. C. M. Berkelaar, Wolfgang Kunz
2002 A conf
Efficient and Effective Redundancy Removal for Million-Gate Circuits.
DATE
Michel R. C. M. Berkelaar, Koen van Eijk
2000 A conf
Gate Sizing Using a Statistical Delay Model.
DATE
E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
1998 A conf
An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization.
DATE
J. W. J. M. Rutten, Michel R. C. M. Berkelaar, C. A. J. van Eijk, M. A. J. Kolsteren
1998 J jnl
Computing observability don't cares efficiently through polarization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Harm Arts, Michel R. C. M. Berkelaar, Koen van Eijk
1998 C conf
Efficient exact and heuristic minimization of hazard-free logic.
ICCD
J. W. J. M. Rutten, Michel R. C. M. Berkelaar
1997 — conf
Improved State Assignment for Burst Mode Finite State Machines.
ASYNC
J. W. J. M. Rutten, Michel R. C. M. Berkelaar
1996 J jnl
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
1996 A conf
Polarized observability don't cares.
ICCAD
Harm Arts, Michel R. C. M. Berkelaar, C. A. J. van Eijk
1995 A conf
Efficient orthonormality testing for synthesis with pass-transistor selectors.
ICCAD
Michel R. C. M. Berkelaar, Lukas P. P. P. van Ginneken
1995 A conf
Efficient use of large don't cares in high-level and logic synthesis.
ICCAD
Reinaldo A. Bergamaschi, Daniel Brand, Leon Stok, Michel R. C. M. Berkelaar, Shiv Prakash
1994 A conf
Computing the entire active area/power consumption versus delay trade-off curve for gate sizing with a piecewise linear simulator.
ICCAD
Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess
1990 — conf
Gate sizing in MOS digital circuits with linear programming.
EURO-DAC
Michel R. C. M. Berkelaar, Jochen A. G. Jess
1988 A conf
Technology mapping for standard-cell generators.
ICCAD
Michel R. C. M. Berkelaar, Jochen A. G. Jess