Michel J. Declercq

46 papers A* 2A 1C 1Misc 2Journal 21Unranked 19
YearRankTypeTitle / Venue / Authors
2011 J jnl
A 0.24-nJ/bit Super-Regenerative Pulsed UWB Receiver in 0.18- μ m CMOS.
IEEE J. Solid State Circuits
Prakash E. Thoppay, Catherine Dehollain, Michael M. Green, Michel J. Declercq
2010 J jnl
Wireless Voltage Regulation for Passive Transponders Using an IF to Communicate.
IEEE Trans. Circuits Syst. I Regul. Pap.
Nicolas Pillin, Norbert Joehl, Catherine Dehollain, Michel J. Declercq
2009 C conf
Load Optimization of an Inductive Power Link for Remote Powering of Biomedical Implants.
ISCAS
Kanber Mithat Silay, Denis Dondi, Luca Larcher, Michel J. Declercq, Luca Benini, Yusuf Leblebici, Catherine Dehollain
2008 — conf
A 7.5mA 500 MHz UWB receiver based on super-regenerative principle.
ESSCIRC
Prakash E. Thoppay, Catherine Dehollain, Michel J. Declercq
2008 Misc conf
Compact Modeling of Suspended Gate FET.
VLSI Design
Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, Christoph Eggimann, Michel J. Declercq, Adrian M. Ionescu
2007 Misc conf
A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling.
VLSI Design
Yogesh Singh Chauhan, François Krummenacher, Renaud Gillon, Benoit Bakeroot, Michel J. Declercq, Adrian M. Ionescu
2006 — conf
A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor.
ISQED
Yogesh Singh Chauhan, Costin Anghel, François Krummenacher, Renaud Gillon, Andre Baguenier, Bart Desoete, Steven Frere, Adrian Mihai Ionescu, Michel J. Declercq
2006 J jnl
A GSM-GPRS/UMTS FDD-TDD/WLAN 802.11a-b-g multi-standard carrier generation system.
IEEE J. Solid State Circuits
Adil Koukab, Yu Lei, Michel J. Declercq
2006 J jnl
Capacitorless 1T DRAM sensing scheme with automatic reference generation.
IEEE J. Solid State Circuits
Marija Blagojevic, Maher Kayal, Marc Pastre, Louis Harik, Michel J. Declercq, Serguei Okhonin, Pierre C. Fazan
2005 J jnl
A model for μ-power rectifier analysis and design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jari-Pascal Curty, Norbert Joehl, François Krummenacher, Catherine Dehollain, Michel J. Declercq
2005 — conf
Multistandard carrier generation system for quad-band GSM/WCDMA (FDD-TDD)/WLAN (802.11 a-b-g) radio.
ESSCIRC
Adil Koukab, Yu Lei, Michel J. Declercq
2005 J jnl
Remotely powered addressable UHF RFID integrated system.
IEEE J. Solid State Circuits
Jari-Pascal Curty, Norbert Joehl, Catherine Dehollain, Michel J. Declercq
2004 J jnl
A fast Modulator for dynamic supply linear RF power amplifier.
IEEE J. Solid State Circuits
Nicolas Schlumpf, Michel J. Declercq, Catherine Dehollain
2004 J jnl
Modeling techniques and verification methodologies for substrate coupling effects in mixed-signal system-on-chip designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Adil Koukab, Kaustav Banerjee, Michel J. Declercq
2003 — conf
A fast modulator for dynamic supply linear RF power amplifier.
ESSCIRC
Nicolas Schlumpf, Michel J. Declercq, Catherine Dehollain
2003 — conf
Frequency-interleaving technique for high-speed A/D conversion.
ISCAS (1)
Guillaume Ding, Catherine Dehollain, Michel J. Declercq, Kamran Azadet
2002 — conf
A SET quantizer circuit aiming at digital communication system.
ISCAS (5)
Santanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq
2002 A conf
Analysis and optimization of substrate noise coupling in single-chip RF transceiver design.
ICCAD
Adil Koukab, Kaustav Banerjee, Michel J. Declercq
2002 A* conf
Few electron devices: towards hybrid CMOS-SET integrated circuits.
DAC
Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier
2002 A* conf
HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC.
DAC
Adil Koukab, Catherine Dehollain, Michel J. Declercq
2002 — conf
Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture.
ISQED
Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine
2002 — conf
SOI Hall effect sensor operating up to 270°C.
CICC
Lionel Portmann, Hussein Ballan, Michel J. Declercq
2001 J jnl
A low-power 1-GHz super-regenerative transceiver with time-shared PLL control.
IEEE J. Solid State Circuits
Norbert Joehl, Catherine Dehollain, Patrick Favre, Philippe Deval, Michel J. Declercq
2001 J jnl
A low-power CMOS super-regenerative receiver at 1 GHz.
IEEE J. Solid State Circuits
Alexandre Vouilloz, Michel J. Declercq, Catherine Dehollain
2000 — conf
A CMOS readout circuit for pico-ampere thin film pyroelectric array detectors.
CICC
Tristan Reimann, François Krummenacher, B. Willing, P. Muralt, Michel J. Declercq
2000 — conf
A low-power CMOS super-regenerative receiver at 1 GHz.
CICC
Alexandre Vouilloz, Catherine Dehollain, Michel J. Declercq
1999 — conf
A 640 mW high accuracy 8-bit 1 GHz flash ADC encoder.
ISCAS (2)
Riad Kanan, François Kaess, Michel J. Declercq
1999 — conf
Modelisation and simulation of integrated super-regenerative receivers.
ICECS
Alexandre Vouilloz, Catherine Dehollain, Michel J. Declercq
1999 J jnl
PCFL3: a low-power, high-speed, single-ended logic family.
IEEE J. Solid State Circuits
Riad Kanan, Michel J. Declercq
1999 — conf
Performance/power tradeoffs in high-speed GaAs ADCs.
ISCAS (2)
François Kaess, Riad Kanan, Bertrand Hochet, Michel J. Declercq
1998 J jnl
A 2-V 600-μA 1-GHz BiCMOS super-regenerative receiver for ISM applications.
IEEE J. Solid State Circuits
Patrick Favre, Norbert Joehl, Alexandre Vouilloz, Philippe Deval, Catherine Dehollain, Michel J. Declercq
1998 J jnl
A high-efficiency CMOS voltage doubler.
IEEE J. Solid State Circuits
Pierre Favrat, Philippe Deval, Michel J. Declercq
1998 — conf
A high-speed BiCMOS switched-current track-and-hold circuit.
CICC
Tristan Reimann, François Krummenacher, Michel J. Declercq
1998 — conf
An automatic offset compensation technique applicable to existing operational amplifier core cell.
CICC
Maher Kayal, R. T. Lara Sáez, Michel J. Declercq
1998 — conf
An overview of the current steering logic (CSL): from the gate to the applications.
ICECS
R. T. Lara Sáez, Maher Kayal, Michel J. Declercq, M. C. Schneider
1997 J jnl
A BiCMOS programmable continuous-time filter using image-parameter method synthesis and voltage-companding technique.
IEEE J. Solid State Circuits
Gilles van Ruymbeke, Christian C. Enz, François Krummenacher, Michel J. Declercq
1997 — conf
EUROPRACTICE and FUSE: the European Commission programmes for supporting education and technology transfer in microelectronics.
MSE
Anne De Baas, Michel J. Declercq
1996 J jnl
An 8-b, 40 msamples/s switched-current-mode track-and-hold circuit on a BiCMOS sea-of-gates array.
IEEE J. Solid State Circuits
Tristan Reimann, François Krummenacher, Michel J. Declercq
1996 — conf
Digital circuit techniques for mixed analog/digital circuits applications.
ICECS
R. T. Lara Sáez, Maher Kayal, Michel J. Declercq, M. C. Schneider
1996 J jnl
Pseudo-complementary FET logic (PCFL): a low-power logic family in GaAs.
IEEE J. Solid State Circuits
Riad Kanan, Bertrand Hochet, Michel J. Declercq
1993 J jnl
Analog circuit implementation on CMOS semi-custom arrays.
IEEE J. Solid State Circuits
Philippe Duchene, Michel J. Declercq, B. Goffart, M. Novak
1992 J jnl
A fast, single-layer, area router for semi-custom analogue circuits.
Int. J. Circuit Theory Appl.
Oscar Buset, Michel J. Declercq, Fouad Rahali, Pascal Vaucher
1992 J jnl
A prototype tool for the design-oriented symbolic analysis of analogue circuits.
Int. J. Circuit Theory Appl.
F. Dorel, Michel J. Declercq
1991 — conf
An integrated layout system for sea-of-gates module generation.
EURO-DAC
Philippe Duchene, Michel J. Declercq, S. M. Kang
1991 J jnl
Implementation of a learning Kohonen neuron based on a new multilevel storage technique.
IEEE J. Solid State Circuits
Bertrand Hochet, Vincent Peiris, Samer Abdo, Michel J. Declercq
1989 J jnl
A highly flexible sea-of-gates structure for digital and analog applications.
IEEE J. Solid State Circuits
Philippe Duchene, Michel J. Declercq