Michael Witterauf

23 papers C 7Misc 1Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2024 C conf
ALPACA: An Accelerator Chip for Nested Loop Programs.
ISCAS
Dominik Walter, Marcel Brand, Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
2021 J jnl
*-Predictable MPSoC execution of real-time control applications using invasive computing.
Concurr. Comput. Pract. Exp.
Marcel Brand, Michael Witterauf, Éricles Sousa, Alexandru Tanase, Frank Hannig, Jürgen Teich
2021 — —
A Compiler for Symbolic Code Generation for Tightly Coupled Processor Arrays.
Michael Witterauf
2021 Misc conf
Aarith: an arbitrary precision number library.
SAC
Oliver Keszöcze, Marcel Brand, Michael Witterauf, Christian Heidorn, Jürgen Teich
2021 J jnl
Symbolic Loop Compilation for Tightly Coupled Processor Arrays.
CoRR
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
2021 J jnl
Symbolic Loop Compilation for Tightly Coupled Processor Arrays.
ACM Trans. Embed. Comput. Syst.
Michael Witterauf, Dominik Walter, Frank Hannig, Jürgen Teich
2020 — conf
Anytime Floating-Point Addition and Multiplication-Concepts and Implementations.
ASAP
Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich
2020 C conf
Real-time Scheduling of I/O Transfers for Massively Parallel Processor Arrays.
MEMOCODE
Dominik Walter, Michael Witterauf, Jürgen Teich
2019 — conf
Anytime instructions for programmable accuracy floating-point arithmetic.
CF
Marcel Brand, Michael Witterauf, Frank Hannig, Jürgen Teich
2019 J jnl
Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays.
J. Comput.
Christian Heidorn, Michael Witterauf, Frank Hannig, Jürgen Teich
2019 C conf
Polyhedral fragments: an efficient representation for symbolically generating code for processor arrays.
MEMOCODE
Michael Witterauf, Frank Hannig, Jürgen Teich
2018 — conf
Invasive Computing for Predictability of Multiple Non-functional Properties: A Cyber-Physical System Case Study.
ASAP
Éricles Sousa, Michael Witterauf, Marcel Brand, Alexandru Tanase, Frank Hannig, Jürgen Teich
2018 C conf
Run-time Requirement Enforcement for Loop Programs on Processor Arrays.
MEMOCODE
Michael Witterauf, Jürgen Teich
2018 J jnl
Symbolic Multi-Level Loop Mapping of Loop Programs for Massively Parallel Processor Arrays.
ACM Trans. Embed. Comput. Syst.
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2017 C conf
Constructing fast and cycle-accurate simulators for configurable accelerators using C++ templates.
RSP
Michael Witterauf, Frank Hannig, Jürgen Teich
2016 — conf
Modulo scheduling of symbolically tiled loops for tightly coupled processor arrays.
ASAP
Michael Witterauf, Alexandru Tanase, Frank Hannig, Jürgen Teich
2016 J jnl
Providing fault tolerance through invasive computing.
it Inf. Technol.
Vahid Lari, Andreas Weichslgartner, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Jürgen Teich, Jan Heißwolf, Stephanie Friederich, Jürgen Becker
2015 — conf
A co-design approach for fault-tolerant loop execution on Coarse-Grained Reconfigurable Arrays.
AHS
Vahid Lari, Alexandru Tanase, Jürgen Teich, Michael Witterauf, Faramarz Khosravi, Frank Hannig, Brett H. Meyer
2015 — conf
Adaptive fault tolerance through invasive computing.
AHS
Michael Witterauf, Alexandru Tanase, Jürgen Teich, Vahid Lari, Andreas Zwinkau, Gregor Snelting
2015 — conf
On-demand fault-tolerant loop processing on massively parallel processor arrays.
ASAP
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig, Vahid Lari
2015 C conf
Symbolic loop parallelization for balancing I/O and memory accesses on processor arrays.
MEMOCODE
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig
2015 J jnl
Techniques for on-demand structural redundancy for massively parallel processor arrays.
J. Syst. Archit.
Vahid Lari, Jürgen Teich, Alexandru Tanase, Michael Witterauf, Faramarz Khosravi, Brett H. Meyer
2014 C conf
Symbolic inner loop parallelisation for massively parallel processor arrays.
MEMOCODE
Alexandru Tanase, Michael Witterauf, Jürgen Teich, Frank Hannig