Michael W. Beattie

15 papers A* 6A 5Journal 4
YearRankTypeTitle / Venue / Authors
2005 A* conf
Spatially distributed 3D circuit models.
DAC
Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter
2004 J jnl
Parasitics extraction with multipole refinement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael W. Beattie, Lawrence T. Pileggi
2002 A* conf
On the efficacy of simplified 2D on-chip inductance models.
DAC
Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
2002 A conf
On-Chip Inductance Models: 3D or Not 3D?
DATE
Tao Lin, Michael W. Beattie, Lawrence T. Pileggi
2002 J jnl
On-chip induction modeling: basics and advanced methods.
IEEE Trans. Very Large Scale Integr. Syst.
Michael W. Beattie, Lawrence T. Pileggi
2002 A conf
Window-Based Susceptance Models for Large-Scale RLC Circuit Analyses.
DATE
Hui Zheng, Lawrence T. Pileggi, Michael W. Beattie, Byron Krauter
2001 A conf
Efficient inductance extraction via windowing.
DATE
Michael W. Beattie, Lawrence T. Pileggi
2001 J jnl
Equipotential shells for efficient inductance extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael W. Beattie, Byron Krauter, Lale Alatan, Lawrence T. Pileggi
2001 A* conf
Inductance 101: Modeling and Extraction.
DAC
Michael W. Beattie, Lawrence T. Pileggi
2001 A* conf
Modeling Magnetic Coupling for On-Chip Interconnect.
DAC
Michael W. Beattie, Lawrence T. Pileggi
2000 A conf
Hierarchical Interconnect Circuit Models.
ICCAD
Michael W. Beattie, Satrajit Gupta, Lawrence T. Pileggi
1999 A conf
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement.
ICCAD
Michael W. Beattie, Lawrence T. Pileggi
1999 J jnl
Error bounds for capacitance extraction via window techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Michael W. Beattie, Lawrence T. Pileggi
1999 A* conf
IC Analyses Including Extracted Inductance Models.
DAC
Michael W. Beattie, Lawrence T. Pileggi
1997 A* conf
Bounds for BEM Capacitance Extraction.
DAC
Michael W. Beattie, Lawrence T. Pileggi