Michael Shebanow

14 papers A* 8B 1Journal 3Unranked 2

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Common Bonds: MIPS, HPS, Two-Level Branch Prediction, and Compressed Code RISC Processor. IEEE Micro Onur Mutlu, Rich Belgard, Thomas R. Gross, Norman P. Jouppi, John L. Hennessy, Steven A. Przybylski, Chris Rowen, Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Tse-Yu Yeh, Andy Wolfe
2016	J	`jnl`	VBTC: GPU-Friendly Variable Block Size Texture Encoding. Comput. Graph. Forum Pavel Krajcevski, Abhinav Golas, K. Ramani, Michael Shebanow, Dinesh Manocha
2013	B	`conf`	Peta Thread Computing [Keynote I]. ISPASS Michael Shebanow
2011	A*	`conf`	Improving GPU performance via large warps and two-level warp scheduling. MICRO Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt
2009	—	`conf`	Pervasive massively multithreaded GPU processors. Conf. Computing Frontiers Michael Shebanow
1995	A*	`conf`	Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. ISCA Mike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey
1991	A*	`conf`	Single Instruction Stream Parallelism is Greater Than Two. ISCA Michael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow
1988	A*	`conf`	Hardware support for large atomic units in dynamically scheduled machines. MICRO Stephen W. Melvin, Michael Shebanow, Yale N. Patt
1987	J	`jnl`	Aquarius. SIGARCH Comput. Archit. News Alvin M. Despain, Yale N. Patt, Vason P. Srini, Philip Bitar, William R. Bush, C. Chien, Wayne Citrin, Barry Fagin, Wenwei Hwu, Stephen W. Melvin, Rick McGeer, Ashok Singhal, Michael Shebanow, Peter Van Roy
1987	A*	`conf`	On tuning the microarchitecture of an HPS implementation of the VAX. MICRO James E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt
1986	—	`conf`	Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. COMPCON Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei
1986	A*	`conf`	Run-time generation of HPS microinstructions from a VAX instruction stream. MICRO Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow, Chein Chen
1985	A*	`conf`	Critical issues regarding HPS, a high performance microarchitecture. MICRO Yale N. Patt, Stephen W. Melvin, Wen-mei W. Hwu, Michael Shebanow
1985	A*	`conf`	HPS, a new microarchitecture: rationale and introduction. MICRO Yale N. Patt, Wen-mei W. Hwu, Michael Shebanow