Michael Schaffner

40 papers A* 2A 5B 1C 6Misc 1Journal 16Unranked 7

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	SYNFI: Pre-Silicon Fault Analysis of an Open-Source Secure Element. CoRR Pascal Nasahl, Miguel Osorio, Pirmin Vogel, Michael Schaffner, Timothy Trippel, Dominic Rizzo, Stefan Mangard
2022	J	`jnl`	SYNFI: Pre-Silicon Fault Analysis of an Open-Source Secure Element. IACR Trans. Cryptogr. Hardw. Embed. Syst. Pascal Nasahl, Miguel Osorio, Pirmin Vogel, Michael Schaffner, Timothy Trippel, Dominic Rizzo, Stefan Mangard
2020	J	`jnl`	Ara: A 1-GHz+ Scalable and Energy-Efficient RISC-V Vector Processor With Multiprecision Floating-Point Support in 22-nm FD-SOI. IEEE Trans. Very Large Scale Integr. Syst. Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2020	A*	`conf`	BYOC: A "Bring Your Own Core" Framework for Heterogeneous-ISA Research. ASPLOS Jonathan Balkind, Katie Lim, Michael Schaffner, Fei Gao, Grigory Chirkov, Ang Li, Alexey Lavrov, Tri M. Nguyen, Yaosheng Fu, Florian Zaruba, Kunal Gulati, Luca Benini, David Wentzlaff
2020	—	`conf`	XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs. COOL CHIPS Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini
2019	J	`jnl`	A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. IEEE Trans. Computers Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2019	J	`jnl`	Ara: A 1 GHz+ Scalable and Energy-Efficient RISC-V Vector Processor with Multi-Precision Floating Point Support in 22 nm FD-SOI. CoRR Matheus A. Cavalcante, Fabian Schuiki, Florian Zaruba, Michael Schaffner, Luca Benini
2019	J	`jnl`	FPGA Implementation of a Kalman-Based Motion Estimator for Levitated Nanoparticles. IEEE Trans. Instrum. Meas. Jiawei Liao, Michael Jost, Michael Schaffner, Michele Magno, Matthias Korb, Luca Benini, Felix Tebbenjohanns, René Reimann, Vijay Jain, Michael Gross, Andrei Militaru, Martin Frimmer, Lukás Novotný
2019	—	`conf`	NTX: A 260 Gflop/sW Streaming Accelerator for Oblivious Floating-Point Algorithms in 22 nm FD-SOI. ISOCC Fabian Schuiki, Michael Schaffner, Luca Benini
2019	A	`conf`	NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22 nm FD-SOI. DATE Fabian Schuiki, Michael Schaffner, Luca Benini
2019	J	`jnl`	Network-Accelerated Non-Contiguous Memory Transfers. CoRR Salvatore Di Girolamo, Konstantin Taranov, Andreas Kurth, Michael Schaffner, Timo Schneider, Jakub Beránek, Maciej Besta, Luca Benini, Duncan Roweth, Torsten Hoefler
2019	A	`conf`	Network-accelerated non-contiguous memory transfers. SC Salvatore Di Girolamo, Konstantin Taranov, Andreas Kurth, Michael Schaffner, Timo Schneider, Jakub Beránek, Maciej Besta, Luca Benini, Duncan Roweth, Torsten Hoefler
2018	J	`jnl`	A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. CoRR Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2018	B	`conf`	An accurate system for optimal state estimation of a levitated nanoparticle. SAS Michael Jost, Michael Schaffner, Michele Magno, Matthias Korb, Luca Benini, René Reimann, Vijay Jain, Michael Gross, Andrei Militaru, Martin Frimmer, Lukás Novotný
2018	J	`jnl`	Design and Evaluation of a Low-Power Sensor Device for Induced Rockfall Experiments. IEEE Trans. Instrum. Meas. Andrin Caviezel, Michael Schaffner, Lukas Cavigelli, Pascal Niklaus, Yves Bühler, Perry Bartelt, Michele Magno, Luca Benini
2018	—	`—`	Energy-efficient VLSI architectures for real-time and 3D video processing. Michael Schaffner
2018	C	`conf`	Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS. ISCAS Manuel Eggimann, Christelle Gloor, Florian Scheidegger, Lukas Cavigelli, Michael Schaffner, Aljosa Smolic, Luca Benini
2018	J	`jnl`	NTX: An Energy-efficient Streaming Accelerator for Floating-point Generalized Reduction Workloads in 22nm FD-SOI. CoRR Fabian Schuiki, Michael Schaffner, Luca Benini
2018	J	`jnl`	On the Feasibility of FPGA Acceleration of Molecular Dynamics Simulations. CoRR Michael Schaffner, Luca Benini
2018	A	`conf`	The transprecision computing paradigm: Concept, design, and applications. DATE A. Cristiano I. Malossi, Michael Schaffner, Anca Molnos, Luca Gammaitoni, Giuseppe Tagliavini, Andrew P. J. Emerson, Andrés Tomás, Dimitrios S. Nikolopoulos, Eric Flamand, Norbert Wehn
2018	J	`jnl`	Towards Edge-Aware Spatio-Temporal Filtering in Real-Time. IEEE Trans. Image Process. Michael Schaffner, Florian Scheidegger, Lukas Cavigelli, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2017	J	`jnl`	An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster. IEEE J. Solid State Circuits Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2017	J	`jnl`	Hydra: An Accelerator for Real-Time Edge-Aware Permeability Filtering in 65nm CMOS. CoRR Manuel Eggimann, Christelle Gloor, Florian Scheidegger, Lukas Cavigelli, Michael Schaffner, Aljosa Smolic, Luca Benini
2017	—	`conf`	Impact of temporal subsampling on accuracy and performance in practical video classification. EUSIPCO Florian Scheidegger, Lukas Cavigelli, Michael Schaffner, A. Cristiano I. Malossi, Constantine Bekas, Luca Benini
2016	—	`conf`	4.6 A 65nm CMOS 6.4-to-29.2pJ/[email protected] shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. ISSCC Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini
2016	C	`conf`	Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters. ARITH Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini
2016	A	`conf`	High-efficiency logarithmic number unit design based on an improved cotransformation scheme. DATE Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini
2016	J	`jnl`	Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. IEEE Trans. Circuits Syst. Video Technol. Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015	C	`conf`	Automatic multiview synthesis - Prototype demo. VCIP Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015	C	`conf`	Automatic multiview synthesis - Towards a mobile system on a chip. VCIP Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic
2015	A	`conf`	DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. DATE Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini
2014	A*	`conf`	An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. DAC Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
2013	—	`conf`	A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. VLSI-SoC (Selected Papers) Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini
2013	C	`conf`	A real-time 720p feature extraction core based on Semantic Kernels Binarized. VLSI-SoC Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin
2013	Misc	`conf`	Efficient image resampling for multiview displays. ICASSP Michael Schaffner, Pierre Greisen, Simon Heinzle, Aljoscha Smolic
2013	—	`conf`	MADmax: A 1080p stereo-to-multiview rendering ASIC in 65 nm CMOS based on image domain warping. ESSCIRC Michael Schaffner, Pierre Greisen, Simon Heinzle, Frank K. Gürkaynak, Hubert Kaeslin, Aljoscha Smolic
2012	C	`conf`	A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. VLSI-SoC Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak
2012	J	`jnl`	Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications. IEEE Trans. Circuits Syst. Video Technol. Pierre Greisen, Michael Schaffner, Simon Heinzle, Marian Runo, Aljoscha Smolic, Andreas Burg, Hubert Kaeslin, Markus H. Gross
2012	—	`conf`	Spatially-Varying Image Warping: Evaluations and VLSI Implementations. VLSI-SoC (Selected Papers) Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic
1996	—	`book`	Methoden zur automatischen Generierung von Simulationsmodellen für ASIC-Bibliotheken. Michael Schaffner