Michael S. Schlansker

36 papers A* 14A 2Misc 2Journal 12Unranked 5

Year	Rank	Type	Title / Venue / Authors
2013	—	`conf`	Configurable optical interconnects for scalable datacenters. OFC/NFOEC Michael S. Schlansker, Michael R. T. Tan, Jean Tourrilhes, Jose Renato Santos, Shih-Yuan Wang
2011	—	`ch.`	Cydra 5. Encyclopedia of Parallel Computing Michael S. Schlansker
2007	A	`conf`	High-performance ethernet-based communications for future multi-core processors. SC Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi
2006	A*	`conf`	Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. MICRO Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder
2005	—	`conf`	A Distributed Control Path Architecture for VLIW Processors. IEEE PACT Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker
2005	J	`jnl`	Fast synchronization for chip multiprocessors. SIGARCH Comput. Archit. News Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker
2003	A*	`conf`	In Memory of Bob Rau. MICRO Michael S. Schlansker
2001	J	`jnl`	Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood
2001	J	`jnl`	Compiling for EPIC architectures. Proc. IEEE Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau
2001	J	`jnl`	Embedded Computer Architecture and Automation. Computer B. Ramakrishna Rau, Michael S. Schlansker
2001	J	`jnl`	Guest Editors' Introduction. J. Instr. Level Parallelism Michael S. Schlansker, Chris J. Newburn
2001	Misc	`conf`	ShiftQ: a bufferred interconnect for custom loop accelerators. CASES Shail Aditya, Michael S. Schlansker
2000	J	`jnl`	EPIC: Explicititly Parallel Instruction Computing. Computer Michael S. Schlansker, B. Ramakrishna Rau
2000	Misc	`conf`	Embedded Computing: New Directions in Architecture and Automation. HiPC B. Ramakrishna Rau, Michael S. Schlansker
2000	A*	`ed.`	Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 33, Monterey, California, USA, December 10-13, 2000 MICRO Andrew Wolfe, Michael S. Schlansker
1999	A*	`conf`	Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. PLDI Michael S. Schlansker, Scott A. Mahlke, Richard Johnson
1997	J	`jnl`	Challenges to Combining General-Purpose and Multimedia Processors. Computer Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe
1997	J	`jnl`	Compilers for Instruction-Level Parallelism. Computer Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson
1997	J	`jnl`	Techniques for critical path reduction of scalar programs. Int. J. Parallel Program. Michael S. Schlansker, Vinod Kathail
1996	A*	`conf`	Analysis Techniques for Predicated Code. MICRO Richard Johnson, Michael S. Schlansker
1996	A*	`conf`	Global Predicate Analysis and Its Application to Register Allocation. MICRO David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker
1996	J	`jnl`	Parallelization of Control Recurrences for ILP Processors. Int. J. Parallel Program. Michael S. Schlansker, Vinod Kathail, Sadun Anik
1996	A*	`conf`	Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker
1995	A*	`conf`	Critical path reduction for scalar programs. MICRO Michael S. Schlansker, Vinod Kathail
1995	A*	`conf`	Spill-free parallel scheduling of basic blocks. MICRO B. Natarajan, Michael S. Schlansker
1994	A*	`conf`	Height reduction of control recurrences for ILP processors. MICRO Michael S. Schlansker, Vinod Kathail, Sadun Anik
1993	—	`conf`	Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC Michael S. Schlansker, Vinod Kathail
1993	J	`jnl`	Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
1992	A*	`conf`	Code generation schema for modulo scheduled loops. MICRO B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai
1992	A*	`conf`	Register Allocation for Software Pipelined Loops. PLDI B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker
1992	A*	`conf`	Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker
1991	J	`jnl`	Parallelization of WHILE loops on pipelined architectures. J. Supercomput. Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker
1990	A	`conf`	Parallelization of loops with exits on pipelined architectures. SC Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker
1989	—	`conf`	The Cydram 5 Stride-Insensitive Memory System. ICPP (1) B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen
1982	—	`conf`	Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker
1973	A*	`conf`	A microprogramming language for the B-1726. MICRO David J. DeWitt, Michael S. Schlansker, Daniel E. Atkins