Michael Pellauer

70 papers A* 18A 6B 3C 6Journal 26Unranked 9
YearRankTypeTitle / Venue / Authors
2026 A* conf
QuCo: Efficient and Flexible Hardware-Driven Automatic Configuration of Tile Transfers in GPUs.
HPCA
Nicolás Meseguer, Daoxuan Xu, Yifan Sun, Michael Pellauer, José L. Abellán, Manuel E. Acacio
2025 — conf
ACTA: Automatic Configuration of the Tensor Memory Accelerator for High-End GPUs.
GPGPU@PPoPP
Nicolás Meseguer, Yifan Sun, Michael Pellauer, José L. Abellán, Manuel E. Acacio
2025 A conf
Cello: Co-Designing Schedule and Hybrid Implicit/Explicit Buffer for Complex Tensor Reuse.
IPDPS
Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam, Tushar Krishna
2025 J jnl
From TeAAL to FuseMax: Separation of Concerns for Attention Accelerator Design.
IEEE Micro
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Xinrui Wu, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
2025 J jnl
HARP: A Taxonomy for Heterogeneous and Hierarchical Processors for Mixed-reuse Workloads.
CoRR
Raveesh Garg, Michael Pellauer, Tushar Krishna
2025 J jnl
HaShiFlex: A High-Throughput Hardened Shifter DNN Accelerator with Fine-Tuning Flexibility.
CoRR
Jonathan Herbst, Michael Pellauer, Sherief Reda
2024 J jnl
Characterizing the Accuracy - Efficiency Trade-off of Low-rank Decomposition in Language Models.
CoRR
Chakshu Moar, Michael Pellauer, Hyoukjun Kwon
2024 — conf
Characterizing the Accuracy-Efficiency Trade-off of Low-rank Decomposition in Language Models.
IISWC
Chakshu Moar, Faraz Tahmasebi, Michael Pellauer, Hyoukjun Kwon
2024 A* conf
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design.
MICRO
Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
2024 J jnl
FuseMax: Leveraging Extended Einsums to Optimize Attention Accelerator Design.
CoRR
Nandeeka Nayak, Xinrui Wu, Toluwanimi O. Odemuyiwa, Michael Pellauer, Joel S. Emer, Christopher W. Fletcher
2024 — conf
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators (Abstract).
HOPC@SPAA
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
2023 — conf
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract).
HOPC@SPAA
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
2023 — conf
Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling.
ASPLOS (3)
Toluwanimi O. Odemuyiwa, Hadi Asghari Moghaddam, Michael Pellauer, Kartik Hegde, Po-An Tsai, Neal Clayton Crago, Aamer Jaleel, John D. Owens, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
2023 J jnl
Exploiting Inter-Operation Data Reuse in Scientific Applications using GOGETA.
CoRR
Raveesh Garg, Michael Pellauer, Sivasankaran Rajamanickam, Tushar Krishna
2023 J jnl
Flexagon: A Multi-Dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.
CoRR
Francisco Muñoz-Martínez, Raveesh Garg, José L. Abellán, Michael Pellauer, Manuel E. Acacio, Tushar Krishna
2023 — conf
Flexagon: A Multi-dataflow Sparse-Sparse Matrix Multiplication Accelerator for Efficient DNN Processing.
ASPLOS (3)
Francisco Muñoz-Martínez, Raveesh Garg, Michael Pellauer, José L. Abellán, Manuel E. Acacio, Tushar Krishna
2023 B conf
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra.
DCC
Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
2023 — conf
Optimizing Compression Schemes for Parallel Sparse Tensor Algebra.
HPEC
Helen Xu, Tao B. Schardl, Michael Pellauer, Joel S. Emer
2023 J jnl
Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing.
ACM Trans. Comput. Syst.
Michael Pellauer, Jason Clemons, Vignesh Balaji, Neal Clayton Crago, Aamer Jaleel, Donghyuk Lee, Mike O'Connor, Anghsuman Parashar, Sean Treichler, Po-An Tsai, Stephen W. Keckler, Joel S. Emer
2023 A* conf
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators.
MICRO
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
2023 J jnl
TeAAL: A Declarative Framework for Modeling Sparse Tensor Accelerators.
CoRR
Nandeeka Nayak, Toluwanimi O. Odemuyiwa, Shubham Ugare, Christopher W. Fletcher, Michael Pellauer, Joel S. Emer
2022 — conf
A Formalism of DNN Accelerator Flexibility.
SIGMETRICS (Abstracts)
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
2022 J jnl
A Formalism of DNN Accelerator Flexibility.
CoRR
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
2022 J jnl
A Formalism of DNN Accelerator Flexibility.
Proc. ACM Meas. Anal. Comput. Syst.
Sheng-Chun Kao, Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
2022 A conf
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators.
DATE
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
2022 J jnl
DiGamma: Domain-aware Genetic Algorithm for HW-Mapping Co-optimization for DNN Accelerators.
CoRR
Sheng-Chun Kao, Michael Pellauer, Angshuman Parashar, Tushar Krishna
2022 J jnl
Enabling Flexibility for Sparse Tensor Acceleration via Heterogeneity.
CoRR
Eric Qin, Raveesh Garg, Abhimanyu Bambhaniya, Michael Pellauer, Angshuman Parashar, Sivasankaran Rajamanickam, Cong Hao, Tushar Krishna
2022 J jnl
Marvel: A Data-Centric Approach for Mapping Deep Learning Operators on Spatial Accelerators.
ACM Trans. Archit. Code Optim.
Prasanth Chatarasi, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Tushar Krishna, Vivek Sarkar
2022 A* conf
Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using ML.
DAC
Ananda Samajdar, Eric Qin, Michael Pellauer, Tushar Krishna
2021 J jnl
Flexion: A Quantitative Metric for Flexibility in DNN Accelerators.
IEEE Comput. Archit. Lett.
Hyoukjun Kwon, Michael Pellauer, Angshuman Parashar, Tushar Krishna
2021 A* conf
Heterogeneous Dataflow Accelerators for Multi-DNN Workloads.
HPCA
Hyoukjun Kwon, Liangzhen Lai, Michael Pellauer, Tushar Krishna, Yu-Hsin Chen, Vikas Chandra
2021 J jnl
Self-Adaptive Reconfigurable Arrays (SARA): Using ML to Assist Scaling GEMM Acceleration.
CoRR
Ananda Samajdar, Michael Pellauer, Tushar Krishna
2020 — book
Data Orchestration in Deep Learning Accelerators
Tushar Krishna, Hyoukjun Kwon, Angshuman Parashar, Michael Pellauer, Ananda Samajdar
2020 J jnl
MAESTRO: A Data-Centric Approach to Understand Reuse, Performance, and Hardware Cost of DNN Mappings.
IEEE Micro
Hyoukjun Kwon, Prasanth Chatarasi, Vivek Sarkar, Tushar Krishna, Michael Pellauer, Angshuman Parashar
2019 A* conf
Buffets: An Efficient and Composable Storage Idiom for Explicit Decoupled Data Orchestration.
ASPLOS
Michael Pellauer, Yakun Sophia Shao, Jason Clemons, Neal Clayton Crago, Kartik Hegde, Rangharajan Venkatesan, Stephen W. Keckler, Christopher W. Fletcher, Joel S. Emer
2019 A* conf
ExTensor: An Accelerator for Sparse Tensor Algebra.
MICRO
Kartik Hegde, Hadi Asghari Moghaddam, Michael Pellauer, Neal Clayton Crago, Aamer Jaleel, Edgar Solomonik, Joel S. Emer, Christopher W. Fletcher
2019 A* conf
Understanding Reuse, Performance, and Hardware Cost of DNN Dataflow: A Data-Centric Approach.
MICRO
Hyoukjun Kwon, Prasanth Chatarasi, Michael Pellauer, Angshuman Parashar, Vivek Sarkar, Tushar Krishna
2018 A* conf
A modular digital VLSI flow for high-productivity SoC design.
DAC
Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer
2018 J jnl
Full-Stack Memory Model Verification with TriCheck.
IEEE Micro
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2018 J jnl
MAESTRO: An Open-source Infrastructure for Modeling Dataflows within Deep Learning Accelerators.
CoRR
Hyoukjun Kwon, Michael Pellauer, Tushar Krishna
2018 A* conf
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition.
ISCA
Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher
2018 J jnl
UCNN: Exploiting Computational Reuse in Deep Neural Networks via Weight Repetition.
CoRR
Kartik Hegde, Jiyong Yu, Rohit Agrawal, Mengjia Yan, Michael Pellauer, Christopher W. Fletcher
2017 A* conf
RTLcheck: verifying the memory consistency of RTL designs.
MICRO
Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer
2017 A* conf
TriCheck: Memory Model Verification at the Trisection of Software, Hardware, and ISA.
ASPLOS
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2016 J jnl
Counterexamples and Proof Loophole for the C/C++ to POWER and ARMv7 Trailing-Sync Compiler Mappings.
CoRR
Yatin A. Manerkar, Caroline Trippel, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2016 J jnl
Exploring the Trisection of Software, Hardware, and ISA in Memory Model Design.
CoRR
Caroline Trippel, Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2015 A* conf
ArMOR: defending against memory consistency model mismatches in heterogeneous architectures.
ISCA
Daniel Lustig, Caroline Trippel, Michael Pellauer, Margaret Martonosi
2015 A* conf
CCICheck: using µhb graphs to verify the coherence-consistency interface.
MICRO
Yatin A. Manerkar, Daniel Lustig, Michael Pellauer, Margaret Martonosi
2015 J jnl
Efficient Control and Communication Paradigms for Coarse-Grained Spatial Architectures.
ACM Trans. Comput. Syst.
Michael Pellauer, Angshuman Parashar, Michael Adler, Bushra Ahsan, Randy L. Allmon, Neal Clayton Crago, Kermin Fleming, Mohit Gambhir, Aamer Jaleel, Tushar Krishna, Daniel Lustig, Stephen Maresh, Vladimir Pavlov, Rachid Rayess, Antonia Zhai, Joel S. Emer
2015 J jnl
Verifying Correct Microarchitectural Enforcement of Memory Consistency Models.
IEEE Micro
Daniel Lustig, Michael Pellauer, Margaret Martonosi
2014 J jnl
Efficient Spatial Processing Element Control via Triggered Instructions.
IEEE Micro
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2014 A* conf
Pipe Check: Specifying and Verifying Microarchitectural Enforcement of Memory Consistency Models.
MICRO
Daniel Lustig, Michael Pellauer, Margaret Martonosi
2013 — conf
A Hierarchical Architectural Framework for Reconfigurable Logic Computing.
IPDPS Workshops
Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel S. Emer
2013 A conf
Heracles: a tool for fast RTL-based design space exploration of multicore processors.
FPGA
Michel A. Kinsy, Michael Pellauer, Srinivas Devadas
2013 A* conf
Triggered instructions: a control paradigm for spatially-programmed architectures.
ISCA
Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer
2012 A conf
Leveraging latency-insensitivity to ease multiple FPGA design.
FPGA
Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer
2011 — —
Cycle-accurate multicore performance models on FPGAs.
Michael Pellauer
2011 A* conf
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing.
HPCA
Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer
2011 B conf
Heracles: Fully Synthesizable Parameterized MIPS-Based Multicore System.
FPL
Michel A. Kinsy, Michael Pellauer, Srinivas Devadas
2011 A conf
Leap scratchpads: automatic memory and cache management for reconfigurable logic.
FPGA
Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer
2010 C conf
A design flow based on modular refinement.
MEMOCODE
Nirav Dave, Man Cheuk Ng, Michael Pellauer, Arvind
2010 C conf
Design contest overview: Combined architecture for network stream categorization and intrusion detection (CANSCID).
MEMOCODE
Michael Pellauer, Abhinav Agarwal, Asif Khan, Man Cheuk Ng, Muralidaran Vijayaraghavan, Forrest Brewer, Joel S. Emer
2009 J jnl
A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2009 A* conf
Soft connections: addressing the hardware-design modularity problem.
DAC
Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer
2008 A conf
A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs.
FPGA
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2008 B conf
Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs.
ISPASS
Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer
2007 C conf
Hardware Acceleration of Matrix Multiplication on a Xilinx FPGA.
MEMOCODE
Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan
2007 C conf
Scheduling as Rule Composition.
MEMOCODE
Nirav Dave, Arvind, Michael Pellauer
2006 C conf
802.11a transmitter: a case study in microarchitectural exploration.
MEMOCODE
Nirav Dave, Michael Pellauer, S. Gerding, Arvind
2005 C conf
Synthesis of synchronous assertions with guarded atomic actions.
MEMOCODE
Michael Pellauer, Mieszko Lis, Don Baltus, Rishiyur S. Nikhil