Michael Payer

17 papers A* 2Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2003 — conf
A Platform for Construction and Integration of Digital IP Blocks.
MBMV
Michael Payer
2001 J jnl
Industrial Experience with Formal Verification (Industrielle Erfahrungen mit Formaler Verifikation).
Informationstechnik Tech. Inform.
Michael Payer
2000 — conf
Industrial Experience with Formal Verification.
MBMV
Michael Payer
1995 A* conf
Model Checking in Industrial Hardware Design.
DAC
Jörg Bormann, Jörg Lohse, Michael Payer, Gerd Venzl
1993 J jnl
The Siemens high-level synthesis system CALLAS.
IEEE Trans. Very Large Scale Integr. Syst.
Jörg Biesenack, Michael Koster, Anton Langmaier, Stephane Ledeux, Sabine März, Michael Payer, Michael Pilsl, Steffen Rumler, Holger Soukup, Norbert Wehn, Peter Duzy
1992 J jnl
Allocation algorithms based on path analysis.
Integr.
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
1992 — conf
Data Part Optimizations in the CALLAS Synthesis Environment.
Synthesis for Control Dominated Circuits
Jörg Biesenack, Norbert Wehn, A. Stoll, Michael Payer
1991 — conf
Area and performance optimizations in path-based scheduling.
EURO-DAC
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
1991 A* conf
Data-Path Synthesis Using Path Analysis.
DAC
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
1991 J jnl
Partitioning and ordering of CMOS circuits for switch level analysis.
Integr.
Michael Payer
1991 J jnl
Scheduling under resource constraints and module assignment.
Integr.
Reinaldo A. Bergamaschi, Raul Camposano, Michael Payer
1989 — conf
Finite State Machine Theory as a Tool for Construction of Systolic Arrays.
EUROCAST
Michael Payer
1989 — —
Graphentheoretische Ansätze für CAD-Werkzeuge in der CMOS-Technik.
Michael Payer
1988 J jnl
A system for estimation of numerical stability for matrix operations in systolic arrays.
Microprocess. Microprogramming
Reinhard H. Rauscher, Peter Kückendahl, Michael Payer
1988 — conf
Hierarchische Zerlegung von Graphen mit zwei ausgezeichneten Knoten mit Anwendugen bei der Synthese und Analyse von MOS-Schaltungen.
GI Jahrestagung (2)
Michael Payer
1987 J jnl
Verification and validation of hierarchical CMOS gate array layouts.
Microprocess. Microprogramming
Michael Payer
1980 — conf
Systematischer Entwurf von Makroprozessoren.
GI Jahrestagung
Michael Payer