Michael P. Flynn

131 papers A 1C 1Misc 1Journal 72Unranked 56

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 175-MHz BW 60-dB SNDR 6th-Order Bandpass Cascaded Time-Interleaved Noise Shaping SAR ADC. IEEE J. Solid State Circuits Zhiyuan Zhao, Hsiang-Wen Chen, Seungheun Song, Taewook Kang, Michael P. Flynn
2026	J	`jnl`	A Multiply-and-Accumulate SAR-ADC-Based Hybrid Slepian Beamformer. IEEE J. Solid State Circuits Zhengqi Xu, Zhiyuan Zhao, Michael A. Laun, Coleman DeLude, Justin Romberg, Michael P. Flynn
2026	—	`conf`	Medusa: A Quantum-Inspired 200-Variable 1016-Clause Analog k-SAT Solver. ISSCC Luke Wormald, Ying-Tuan Hsu, Evangelos Dikopoulos, Wei Tang, Benjamin Datsko, Ali Hammoud, Zhengya Zhang, Michael P. Flynn
2025	—	`conf`	25.1 A Physics-Inspired Oscillator-Based Mixed-Signal Optimization Engine for Solving 50-Variable 218-Clause 3-SAT Problems with 100 ISSCC Evangelos Dikopoulos, Ying-Tuan Hsu, Luke Wormald, Wei Tang, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	A Digital-Sampling PLL With a Second-Order Noise Shaping SAR ADC Phase Detector. IEEE J. Solid State Circuits Matthew R. Belz, Zhengqi Xu, Hsiang-Wen Chen, Seungheun Song, Michael P. Flynn
2025	J	`jnl`	An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. IEEE J. Solid State Circuits Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Wei D. Lu, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	Daedalus: A Physics-Inspired Mixed-Signal Optimization Engine With Dynamic Continuous-Time Injection for Solving 3-SAT Problems. IEEE J. Solid State Circuits Evangelos Dikopoulos, Ying-Tuan Hsu, Luke Wormald, Wei Tang, Benjamin Datsko, Zhengya Zhang, Michael P. Flynn
2025	J	`jnl`	RXO-LDPC: A Physics-Inspired Relaxation Oscillator-Based Solver Leveraging Six-Body Spin Interactions for Soft Decoding of LDPC Codes. IEEE J. Solid State Circuits Evangelos Dikopoulos, Luke Wormald, Ying-Tuan Hsu, Wei Tang, Po-Shao Chen, Zhengya Zhang, Michael P. Flynn
2024	—	`conf`	A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental sΔΔ Neural Recording Frontend with Resolution-Preservative 192mV/ms Transient Tracking. VLSI Technology and Circuits Sungjin Oh, Hyunsoo Song, Jose Roberto Lopez Ruiz, Wangbo Chen, Sung-Yun Park, Michael P. Flynn, Euisik Yoon
2024	J	`jnl`	A Multimode 157 μW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive Beamformer. IEEE J. Solid State Circuits Taewook Kang, Seungjong Lee, Seungheun Song, Mohammad Reza Haghighat, Michael P. Flynn
2024	J	`jnl`	An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer. IEEE J. Solid State Circuits Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn
2023	—	`conf`	A 0.024mm² 84.2dB-SNDR 1MHz-BW 3 VLSI Technology and Circuits Hsiang-Wen Chen, Seungjong Lee, Michael P. Flynn
2023	—	`conf`	A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C. VLSI Technology and Circuits Seungheun Song, Taewook Kang, Seungjong Lee, Michael P. Flynn
2023	J	`jnl`	A Direct Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Rundao Lu, Michael P. Flynn
2023	J	`jnl`	An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. IEEE J. Solid State Circuits Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn
2022	—	`conf`	6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration. ESSCIRC Evelyn Ware, Justin M. Correll, Seungjong Lee, Michael P. Flynn
2022	—	`conf`	A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer. ISSCC Taewook Kang, Seungjong Lee, Seungheun Song, Mohammad R. Haghighat, Michael P. Flynn
2022	—	`conf`	An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. VLSI Technology and Circuits Justin M. Correll, Lu Jie, Seungheun Song, Seungjong Lee, Junkang Zhu, Wei Tang, Luke Wormald, Jack Erhardt, Nicolas Breil, Roger Quon, Deepak Kamalanathan, Siddarth A. Krishnan, Michael Chudzik, Zhengya Zhang, Wei D. Lu, Michael P. Flynn
2022	—	`conf`	An 81.6dB SNDR 15.625MHz BW 3 VLSI Technology and Circuits Seungjong Lee, Taewook Kang, Seungheun Song, Kyumin Kwon, Michael P. Flynn
2022	J	`jnl`	An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor. IEEE J. Solid State Circuits Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn
2022	J	`jnl`	TAICHI: A Tiled Architecture for In-Memory Computing and Heterogeneous Integration. IEEE Trans. Circuits Syst. II Express Briefs Xinxin Wang, Reid Pinkham, Mohammed Affan Zidan, Fan-Hsuan Meng, Michael P. Flynn, Zhengya Zhang, Wei D. Lu
2021	—	`conf`	10.3 A 100MHz-BW 68dB-SNDR Tuning-Free Hybrid-Loop DSM with an Interleaved Bandpass Noise-Shaping SAR Quantizer. ISSCC Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
2021	J	`jnl`	A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver. IEEE J. Solid State Circuits Rundao Lu, Christine Weston, Daniel Weyer, Fred N. Buhler, Daniel Lambalot, Michael P. Flynn
2021	J	`jnl`	A 17.8-MS/s Compressed Sensing Radar Accelerator Using a Spiking Neural Network. IEEE J. Solid State Circuits Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher Rozell, Justin Romberg, Michael P. Flynn
2021	—	`conf`	A 300MHz-BW 38mW 37dB/40dB SNDR/DR Frequency-Interleaving Continuous-Time Bandpass Delta-Sigma ADC in 28nm CMOS. VLSI Circuits Rundao Lu, Michael P. Flynn
2021	—	`conf`	A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction. CICC Taewook Kang, Seungjong Lee, Mohammad Haghigat, Darren Abramson, Michael P. Flynn
2021	J	`jnl`	A Hybrid-Loop Structure and Interleaved Noise-Shaped Quantizer for a Robust 100-MHz BW and 69-dB DR DSM. IEEE J. Solid State Circuits Lu Jie, Hsiang-Wen Chen, Boyi Zheng, Michael P. Flynn
2021	J	`jnl`	Erratum to "A 16-Element Fully Integrated 28-GHz Digital RX Beamforming Receiver". IEEE J. Solid State Circuits Rundao Lu, Christine Weston, Daniel Weyer, Fred N. Buhler, Daniel Lambalot, Michael P. Flynn
2021	—	`conf`	TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping. ESSCIRC Boyi Zheng, Lu Jie, Michael P. Flynn
2020	—	`conf`	9.4 A 4 ISSCC Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Runyu Wang, Michael P. Flynn
2020	—	`conf`	A 17.8MS/s Neural-Network Compressed Sensing Radar Processor in 16nm FinFET CMOS. CICC Peter Lawrence Brown, Matthew R. O'Shaughnessy, Christopher J. Rozell, Justin Romberg, Michael P. Flynn
2020	J	`jnl`	A Cascaded Noise-Shaping SAR Architecture for Robust Order Extension. IEEE J. Solid State Circuits Lu Jie, Boyi Zheng, Hsiang-Wen Chen, Michael P. Flynn
2020	—	`conf`	An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy. VLSI Circuits Seungjong Lee, Taewook Kang, John Bell, Mohammad R. Haghighat, Alberto J. Martinez, Michael P. Flynn
2020	—	`conf`	Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited). CICC Michael P. Flynn, Jaehun Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu, John Bell
2019	J	`jnl`	A 1-GHz 16-Element Four-Beam True-Time-Delay Digital Beamformer. IEEE J. Solid State Circuits Sunmin Jang, Rundao Lu, Jaehun Jeong, Michael P. Flynn
2019	—	`conf`	A 50MHz-Bandwidth 70.4dB-SNDR Calibration-Free Time-Interleaved 4 ISSCC Lu Jie, Boyi Zheng, Michael P. Flynn
2019	J	`jnl`	A Calibration-Free Time-Interleaved Fourth-Order Noise-Shaping SAR ADC. IEEE J. Solid State Circuits Lu Jie, Boyi Zheng, Michael P. Flynn
2019	—	`conf`	A Simultaneous Multiband Continuous-Time ΔΣ ADC With 90-MHz Aggregate Bandwidth in 40-nm CMOS. ESSCIRC John Bell, Michael P. Flynn
2019	J	`jnl`	Design Considerations for Integrated Radar Chirp Synthesizers. IEEE Access Daniel Weyer, Mehmet Batuhan Dayanik, Lu Jie, Ahmed Albalawi, Abdulhamed Alothaimen, Mohammed Aseeri, Michael P. Flynn
2018	J	`jnl`	A 16-Element 4-Beam 1 GHz IF 100 MHz Bandwidth Interleaved Bit Stream Digital Beamformer in 40 nm CMOS. IEEE J. Solid State Circuits Sunmin Jang, Jaehun Jeong, Rundao Lu, Michael P. Flynn
2018	—	`conf`	A 36.3-to-38.2GHz -216dBc/Hz ISSCC Daniel Weyer, Mehmet Batuhan Dayanik, Sunmin Jang, Michael P. Flynn
2018	—	`conf`	A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping. VLSI Circuits Adam E. Mendrela, Sung-Yun Park, Mihály Vöröslakos, Michael P. Flynn, Euisik Yoon
2018	J	`jnl`	A Maximum-Likelihood Sequence Detection Powered ADC-Based Serial Link. IEEE Trans. Circuits Syst. I Regul. Pap. Shiming Song, Kyojin David Choo, Thomas Chen, Sunmin Jang, Michael P. Flynn, Zhengya Zhang
2018	J	`jnl`	A Mismatch-Immune 12-Bit SAR ADC With Completely Reconfigurable Capacitor DAC. IEEE Trans. Circuits Syst. II Express Briefs Nicholas Collins, Andres Tamez, Lu Jie, Jorge Pernillo, Michael P. Flynn
2018	J	`jnl`	Digital Fractional-N PLLs Based on a Continuous-Time Third-Order Noise-Shaping Time-to-Digital Converter for a 240-GHz FMCW Radar System. IEEE J. Solid State Circuits Mehmet Batuhan Dayanik, Michael P. Flynn
2017	J	`jnl`	A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging. IEEE J. Solid State Circuits John Bell, Phil Knag, Shuanghong Sun, Yong Lim, Thomas Chen, Jeffrey Fredenburg, Chia-Hsiang Chen, Chunyang Zhai, Aaron Z. Rocca, Nicholas Collins, Andres Tamez, Jorge Pernillo, Justin M. Correll, Alan B. Tanner, Zhengya Zhang, Michael P. Flynn
2017	J	`jnl`	A 48-MHz Differential Crystal Oscillator With 168-fs Jitter in 28-nm CMOS. IEEE J. Solid State Circuits Yashar Rajavi, Mohammad Mahdi Ghahramani, Alireza Khalili, Amirpouya Kavousian, Beomsup Kim, Michael P. Flynn
2016	—	`conf`	27.3 Area-efficient 1GS/s 6b SAR ADC with charge-injection-cell-based DAC. ISSCC Kyojin David Choo, John Bell, Michael P. Flynn
2016	—	`conf`	A 16-channel noise-shaping machine learning analog-digital interface. VLSI Circuits Fred N. Buhler, Adam E. Mendrela, Yong Lim, Jeffrey A. Fredenburg, Michael P. Flynn
2016	J	`jnl`	A 260 MHz IF Sampling Bit-Stream Processing Digital Beamformer With an Integrated Array of Continuous-Time Band-Pass ΔΣ Modulators. IEEE J. Solid State Circuits Jaehun Jeong, Nicholas Collins, Michael P. Flynn
2016	J	`jnl`	A 69 dB SNDR, 25 MHz BW, 800 MS/s Continuous-Time Bandpass ΔΣ Modulator Using a Duty-Cycle-Controlled DAC for Low Power and Reconfigurability. IEEE J. Solid State Circuits Hyungil Chae, Michael P. Flynn
2016	J	`jnl`	A Bidirectional Neural Interface Circuit With Active Stimulation Artifact Cancellation and Cross-Channel Common-Mode Noise Suppression. IEEE J. Solid State Circuits Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Vivek Nagaraj, Theoden I. Netoff, Michael P. Flynn, Euisik Yoon
2016	J	`jnl`	Introducing BrowZine, a Tablet and Phone-Based Reader for the JSSC. IEEE J. Solid State Circuits Michael P. Flynn
2016	J	`jnl`	Introducing Short Regular Papers. IEEE J. Solid State Circuits Michael P. Flynn
2016	J	`jnl`	Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits Michael P. Flynn
2016	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2016	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Michael P. Flynn, Pietro Andreani, SeongHwan Cho
2015	—	`conf`	26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC. ISSCC Yong Lim, Michael P. Flynn
2015	J	`jnl`	A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC. IEEE J. Solid State Circuits Yong Lim, Michael P. Flynn
2015	J	`jnl`	A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers. IEEE J. Solid State Circuits Yong Lim, Michael P. Flynn
2015	—	`conf`	A 28.5-33.5GHz fractional-N PLL using a 3 ESSCIRC Mehmet Batuhan Dayanik, Nicholas Collins, Michael P. Flynn
2015	—	`conf`	ADC trends and impact on SAR ADC architecture and analysis. CICC Jeffrey Fredenburg, Michael P. Flynn
2015	—	`conf`	Enabling closed-loop neural interface: A bi-directional interface circuit with stimulation artifact cancellation and cross-channel CM noise suppression. VLSIC Adam E. Mendrela, Jihyun Cho, Jeffrey A. Fredenburg, Cynthia A. Chestek, Michael P. Flynn, Euisik Yoon
2015	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2015	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2015	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2015	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2015	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Michael P. Flynn
2014	—	`conf`	11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers. ISSCC Yong Lim, Michael P. Flynn
2014	J	`jnl`	A 12 mW Low Power Continuous-Time Bandpass ΔΣ Modulator With 58 dB SNDR and 24 MHz Bandwidth at 200 MHz IF. IEEE J. Solid State Circuits Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
2014	J	`jnl`	A Fully Self-Contained Logarithmic Closed-Loop Deep Brain Stimulation SoC With Wireless Telemetry and Wireless Power Management. IEEE J. Solid State Circuits Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn
2014	—	`conf`	An N-path filter enhanced low phase noise ring VCO. VLSIC Chunyang Zhai, Jeffrey Fredenburg, John Bell, Michael P. Flynn
2014	J	`jnl`	New Associate Editor [Ken Suyama]. IEEE J. Solid State Circuits Michael P. Flynn
2014	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2014	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2014	J	`jnl`	New Associate Editors. IEEE J. Solid State Circuits Michael P. Flynn
2013	—	`conf`	A 9b 2GS/s 45mW 2X-interleaved ADC. ESSCIRC Jorge Pernillo, Michael P. Flynn
2013	—	`conf`	EP2: You're hired! The top 25 interview questions for circuit designers. ISSCC Michael P. Flynn, John Khoury
2013	J	`jnl`	Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits Michael P. Flynn
2013	J	`jnl`	New Associate Editor. IEEE J. Solid State Circuits Michael P. Flynn
2012	—	`conf`	A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF. ISSCC Hyungil Chae, Jaehun Jeong, Gabriele Manganaro, Michael P. Flynn
2012	—	`conf`	A 22Gb/s, 10mm on-chip serial link over lossy transmission line with resistive termination. ESSCIRC Hyo Gyuem Rhew, Michael P. Flynn, Junyoung Park
2012	J	`jnl`	A 90-MS/s 11-MHz-Bandwidth 62-dB SNDR Noise-Shaping SAR ADC. IEEE J. Solid State Circuits Jeffrey Fredenburg, Michael P. Flynn
2012	—	`conf`	A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC. ISSCC Jeffrey Fredenburg, Michael P. Flynn
2012	J	`jnl`	A Flexible 500 MHz to 3.6 GHz Wireless Receiver with Configurable DT FIR and IIR Filter Embedded in a 7b 21 MS/s SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn
2012	J	`jnl`	A Low-Power Compressive Sampling Time-Based Analog-to-Digital Converter. IEEE J. Emerg. Sel. Topics Circuits Syst. Praveen K. Yenduri, Aaron Z. Rocca, Aswin S. Rao, Shahrzad Naraghi, Michael P. Flynn, Anna C. Gilbert
2012	—	`conf`	A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders. VLSIC Hyo-Gyuem Rhew, Jaehun Jeong, Jeffrey A. Fredenburg, Sunjay Dodani, Parag G. Patil, Michael P. Flynn
2012	J	`jnl`	Statistical Analysis of ENOB and Yield in Binary Weighted ADCs and DACS With Random Element Mismatch. IEEE Trans. Circuits Syst. I Regul. Pap. Jeffrey Fredenburg, Michael P. Flynn
2011	J	`jnl`	A 1.5-GS/s Flash ADC With 57.7-dB SFDR and 6.4-Bit ENOB in 90 nm Digital CMOS. IEEE Trans. Circuits Syst. II Express Briefs Jorge Pernillo, Michael P. Flynn
2011	J	`jnl`	A 14 b 23 MS/s 48 mW Resetting Sigma Delta ADC. IEEE Trans. Circuits Syst. I Regul. Pap. Chun C. Lee, Michael P. Flynn
2011	J	`jnl`	A SAR-Assisted Two-Stage Pipeline ADC. IEEE J. Solid State Circuits Chun C. Lee, Michael P. Flynn
2011	Misc	`conf`	Rand PPM: A lowpower compressive sampling analog to digital converter. ICASSP Praveen K. Yenduri, Anna C. Gilbert, Michael P. Flynn, Shahrzad Naraghi
2010	J	`jnl`	A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC. IEEE J. Solid State Circuits Jongwoo Lee, Hyo-Gyuem Rhew, Daryl R. Kipke, Michael P. Flynn
2010	J	`jnl`	A 9-bit, 14 μW and 0.06 mm IEEE J. Solid State Circuits Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn
2010	—	`conf`	A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC. CICC David T. Lin, Li Li, Shahin Farahani, Michael P. Flynn
2010	—	`conf`	An integrated 120 volt AC mains voltage interface in standard 130 nm CMOS. ESSCIRC Andres Tamez, Jeffrey A. Fredenburg, Michael P. Flynn
2009	J	`jnl`	A 2.5 mW 80 dB DR 36 dB SNDR 22 MS/s Logarithmic Pipeline ADC. IEEE J. Solid State Circuits Jongwoo Lee, Joshua Jaeyoung Kang, Sunghyun Park, Jae-sun Seo, Jens Anders, Jorge Guilherme, Michael P. Flynn
2009	J	`jnl`	A 9-Gbit/s Serial Transceiver for On-Chip Global Signaling Over Lossy Transmission Lines. IEEE Trans. Circuits Syst. I Regul. Pap. Junyoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn
2009	—	`conf`	A 9b 14µW 0.06mm ISSCC Shahrzad Naraghi, Matthew Courcy, Michael P. Flynn
2009	—	`conf`	A fractional-N PLL modulator with flexible direct digital phase modulation. CICC Mark A. Ferriss, David T. Lin, Michael P. Flynn
2008	J	`jnl`	A 14 mW Fractional-N PLL Modulator With a Digital Phase Detector and Frequency Switching Scheme. IEEE J. Solid State Circuits Mark A. Ferriss, Michael P. Flynn
2008	—	`conf`	A 9Gbit/s serial transceiver for on-chip global signaling over lossy transmission lines. CICC Junyoung Park, Joshua Jaeyoung Kang, Sunghyun Park, Michael P. Flynn
2008	—	`conf`	A reconfigurable FIR filter embedded in a 9b successive approximation ADC. CICC Joshua Jaeyoung Kang, David T. Lin, Li Li, Michael P. Flynn
2007	—	`conf`	A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme. ISSCC Mark A. Ferriss, Michael P. Flynn
2007	J	`jnl`	A 4-GS/s 4-bit Flash ADC in 0.18-µm CMOS. IEEE J. Solid State Circuits Sunghyun Park, Yorgos Palaskas, Michael P. Flynn
2007	—	`conf`	A 57 dB SFDR digitally calibrated 500 MS/s folding ADC in 0.18 μm digital CMOS. CICC Ivan Bogue, Michael P. Flynn
2007	J	`jnl`	A Fully Integrated Auto-Calibrated Super-Regenerative Receiver in 0.13-µm CMOS. IEEE J. Solid State Circuits Jia-Yi Chen, Michael P. Flynn, John P. Hayes
2006	—	`conf`	A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS. CICC Sunghyun Park, Yorgos Palaskas, Ashoke Ravi, Ralph E. Bishop, Michael P. Flynn
2006	—	`conf`	A 4GS/s 4b Flash ADC in 0.18µm CMOS. ISSCC Sunghyun Park, Yorgos Palaskas, Michael P. Flynn
2006	—	`conf`	A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. ISSCC Jia-Yi Chen, Michael P. Flynn, John P. Hayes
2006	—	`conf`	A Low Jitter Multi-Phase PLL with Capacitive Coupling. CICC Junyoung Park, Michael P. Flynn
2006	J	`jnl`	A new transponder architecture with on-chip ADC for long-range telemetry applications. IEEE J. Solid State Circuits Fatih Kocer, Michael P. Flynn
2006	J	`jnl`	A regenerative comparator structure with integrated inductors. IEEE Trans. Circuits Syst. I Regul. Pap. Sunghyun Park, Michael P. Flynn
2005	—	`conf`	A 3.6mW 2.4-GHz multi-channel super-regenerative receiver in 130nm CMOS. CICC Jia-Yi Chen, Michael P. Flynn, John P. Hayes
2005	—	`conf`	A new transponder architecture for long-range telemetry applications. ECCTD Fatih Kocer, Michael P. Flynn
2005	—	`conf`	Capacitively averaged multi-phase LC oscillators. ISCAS (3) Junyoung Park, Michael P. Flynn
2005	—	`conf`	Design techniques for high performance CMOS flash analog-to-digital converters. ECCTD Sunghyun Park, Michael P. Flynn
2005	A	`conf`	Global signaling over lossy transmission lines. ICCAD Michael P. Flynn, Joshua Jaeyoung Kang
2004	—	`conf`	An RF powered, wireless temperature sensor in quarter micron CMOS. ISCAS (4) Fatih Kocer, Paul M. Walsh, Michael P. Flynn
2003	J	`jnl`	Digital calibration incorporating redundancy of flash ADCs. IEEE Trans. Circuits Syst. II Express Briefs Michael P. Flynn, Conor Donovan, L. Sattler
2002	J	`jnl`	A "digital" 6-bit ADC in 0.25-μm CMOS. IEEE J. Solid State Circuits Conor Donovan, Michael P. Flynn
2002	J	`jnl`	A low-power 8-PAM serial transceiver in 0.5-μm digital CMOS. IEEE J. Solid State Circuits David J. Foley, Michael P. Flynn
2001	—	`conf`	A 'digital' 6-bit ADC in 0.25 μm CMOS. CICC Conor Donovan, Michael P. Flynn
2001	—	`conf`	A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS. CICC David J. Foley, Michael P. Flynn
2001	J	`jnl`	CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator. IEEE J. Solid State Circuits David J. Foley, Michael P. Flynn
2000	C	`conf`	A 3.3 V, 1.6 GHz, low-jitter, self-correcting DLL based clock synthesizer in 0.5 μm CMOS. ISCAS David J. Foley, Michael P. Flynn
2000	—	`conf`	CMOS DLL based 2 V, 3.2 ps jitter, 1 GHz clock synthesizer and temperature compensated tunable oscillator. CICC David J. Foley, Michael P. Flynn
1999	—	`conf`	A BiCMOS preamplifier/write-driver IC for tape drive. CICC Michael P. Flynn, Michael Twohig, Raymond Byrne, Hooman Reyhani, John Ryan
1998	J	`jnl`	A 400-Msample/s, 6-b CMOS folding and interpolating ADC. IEEE J. Solid State Circuits Michael P. Flynn, Ben Sheahan
1996	J	`jnl`	CMOS folding A/D converters with current-mode interpolation. IEEE J. Solid State Circuits Michael P. Flynn, David J. Allstot
1992	J	`jnl`	A 1.2- mu m CMOS current-controlled oscillator. IEEE J. Solid State Circuits Michael P. Flynn, Sverre U. Lidholm