Michael Orshansky

100 papers A* 13A 25B 1C 2Misc 1Journal 31Unranked 26

Year	Rank	Type	Title / Venue / Authors
2025	A*	`conf`	Mixed-Precision Quantization for Deep Vision Models with Integer Quadratic Programming. DAC Zihao Deng, Sayeh Sharify, Xin Wang, Michael Orshansky
2025	J	`jnl`	Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption. CoRR Yeonsoo Jeon, Mattan Erez, Michael Orshansky
2024	J	`jnl`	A Hierarchical Classification Method for High-accuracy Instruction Disassembly with Near-field EM Measurements. ACM Trans. Embed. Comput. Syst. Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Andreas Gerstlauer, Ali E. Yilmaz
2024	—	`conf`	SoK Paper: Power Side-Channel Malware Detection. HASP@MICRO Alexander Cathis, Ge Li, Shijia Wei, Michael Orshansky, Mohit Tiwari, Andreas Gerstlauer
2023	J	`jnl`	A Provably Secure Strong PUF Based on LWE: Construction and Implementation. IEEE Trans. Computers Xiaodan Xi, Ge Li, Ye Wang, Michael Orshansky
2023	J	`jnl`	A Provably Secure Strong PUF based on LWE: Construction and Implementation. CoRR Xiaodan Xi, Ge Li, Ye Wang, Yeonsoo Jeon, Michael Orshansky
2023	J	`jnl`	Artemis: HE-Aware Training for Efficient Privacy-Preserving Machine Learning. CoRR Yeonsoo Jeon, Mattan Erez, Michael Orshansky
2023	C	`conf`	Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training. ACML Zihao Deng, Benjamin Ghaemmaghami, Ashish Kumar Singh, Benjamin Y. Cho, Leo Orshansky, Mattan Erez, Michael Orshansky
2023	J	`jnl`	Enhancing Cross-Category Learning in Recommendation Systems with Multi-Layer Embedding Training. CoRR Zihao Deng, Benjamin Ghaemmaghami, Ashish Kumar Singh, Benjamin Y. Cho, Leo Orshansky, Mattan Erez, Michael Orshansky
2023	J	`jnl`	Mixed-Precision Quantization with Cross-Layer Dependencies. CoRR Zihao Deng, Xin Wang, Sayeh Sharify, Michael Orshansky
2022	—	`conf`	High-Level Simulation of Embedded Software Vulnerabilities to EM Side-Channel Attacks. SAMOS Aditya Thimmaiah, Vishnuvardhan V. Iyer, Andreas Gerstlauer, Michael Orshansky
2022	J	`jnl`	Power-based Attacks on Spatial DNN Accelerators. ACM J. Emerg. Technol. Comput. Syst. Ge Li, Mohit Tiwari, Michael Orshansky
2022	A	`conf`	Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. DATE Zihao Deng, Michael Orshansky
2021	—	`conf`	Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management. CICC Meizhi Wang, Shanshan Xie, Ping Na Li, Aseem Sayal, Ge Li, Vishnuvardhan V. Iyer, Aditya Thimmaiah, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
2021	J	`jnl`	Horizontal Side-Channel Vulnerabilities of Post-Quantum Key Exchange and Encapsulation Protocols. ACM Trans. Embed. Comput. Syst. Furkan Aydin, Aydin Aysu, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky
2021	—	`conf`	Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks. CICC Meizhi Wang, Vishnuvardhan V. Iyer, Shanshan Xie, Ge Li, Sanu K. Mathew, Raghavan Kumar, Michael Orshansky, Ali E. Yilmaz, Jaydeep P. Kulkarni
2021	J	`jnl`	Power-Based Attacks on Spatial DNN Accelerators. CoRR Ge Li, Mohit Tiwari, Michael Orshansky
2021	J	`jnl`	Variability-Aware Training and Self-Tuning of Highly Quantized DNNs for Analog PIM. CoRR Zihao Deng, Michael Orshansky
2020	J	`jnl`	A Strong Subthreshold Current Array PUF Resilient to Machine Learning Attacks. IEEE Trans. Circuits Syst. I Regul. Pap. Haoyu Zhuang, Xiaodan Xi, Nan Sun, Michael Orshansky
2020	—	`conf`	Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks. HOST Ye Wang, Xiaodan Xi, Michael Orshansky
2020	J	`jnl`	Training with Multi-Layer Embeddings for Model Reduction. CoRR Benjamin Ghaemmaghami, Zihao Deng, Benjamin Y. Cho, Leo Orshansky, Ashish Kumar Singh, Mattan Erez, Michael Orshansky
2019	J	`jnl`	Lattice PUF: A Strong Physical Unclonable Function Provably Secure against Machine Learning Attacks. CoRR Ye Wang, Xiaodan Xi, Michael Orshansky
2019	—	`conf`	Securing AES against Localized EM Attacks through Spatial Randomization of Dataflow. HOST Ge Li, Vishnuvardhan V. Iyer, Michael Orshansky
2019	—	`conf`	Using Power-Anomalies to Counter Evasive Micro-Architectural Attacks in Embedded Systems. HOST Shijia Wei, Aydin Aysu, Michael Orshansky, Andreas Gerstlauer, Mohit Tiwari
2018	A	`conf`	Binary Ring-LWE hardware with power side-channel countermeasures. DATE Aydin Aysu, Michael Orshansky, Mohit Tiwari
2018	A	`conf`	Efficient helper data reduction in SRAM PUFs via lossy compression. DATE Ye Wang, Michael Orshansky
2018	—	`conf`	Fresh re-keying with strong PUFs: A new approach to side-channel security. HOST Xiaodan Xi, Aydin Aysu, Michael Orshansky
2018	—	`conf`	Horizontal side-channel vulnerabilities of post-quantum key exchange protocols. HOST Aydin Aysu, Youssef Tobah, Mohit Tiwari, Andreas Gerstlauer, Michael Orshansky
2017	—	`conf`	A new maskless debiasing method for lightweight physical unclonable functions. HOST Aydin Aysu, Ye Wang, Patrick Schaumont, Michael Orshansky
2017	A	`conf`	Efficient simulation of EM side-channel attack resilience. ICCAD Amit Kumar, Cody Scarborough, Ali E. Yilmaz, Michael Orshansky
2016	A*	`conf`	A Monte Carlo simulation flow for SEU analysis of sequential circuits. DAC Meng Li, Ye Wang, Michael Orshansky
2016	A	`conf`	Exploiting randomness in sketching for efficient hardware implementation of machine learning applications. ICCAD Ye Wang, Constantine Caramanis, Michael Orshansky
2016	—	`conf`	Multiple Attempt Write Strategy for Low Energy STT-RAM. ACM Great Lakes Symposium on VLSI Jaeyoung Park, Michael Orshansky
2016	A	`conf`	PolyGP: Improving GP-based analog optimization through accurate high-order monomials and semidefinite relaxation. DATE Ye Wang, Constantine Caramanis, Michael Orshansky
2016	J	`jnl`	Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture. IEEE Trans. Very Large Scale Integr. Syst. Jaeyoung Park, Tianhao Zheng, Mattan Erez, Michael Orshansky
2015	A*	`conf`	Novel power grid reduction method based on L1 regularization. DAC Ye Wang, Meng Li, Xinyang Yi, Zhao Song, Michael Orshansky, Constantine Caramanis
2014	A*	`conf`	Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization. DAC Ye Wang, Michael Orshansky, Constantine Caramanis
2014	J	`jnl`	Modeling and Optimization Techniques for Yield-Aware SRAM Post-Silicon Tuning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky
2014	A	`conf`	Multi-level approximate logic synthesis under general error constraints. ICCAD Jin Miao, Andreas Gerstlauer, Michael Orshansky
2013	B	`conf`	Approximate computing: An emerging paradigm for energy-efficient design. ETS Jie Han, Michael Orshansky
2013	A	`conf`	Approximate logic synthesis under general error magnitude and frequency constraints. ICCAD Jin Miao, Andreas Gerstlauer, Michael Orshansky
2013	J	`jnl`	Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems. IEEE Trans. Circuits Syst. Video Technol. Ku He, Andreas Gerstlauer, Michael Orshansky
2013	A*	`conf`	Gene modification identification under flux capacity uncertainty. DAC Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun
2013	—	`conf`	Low-energy digital filter design based on controlled timing error acceptance. ISQED Ku He, Andreas Gerstlauer, Michael Orshansky
2013	—	`conf`	Novel strong PUF based on nonlinearity of MOSFET subthreshold operation. HOST Mukund Kalyanaraman, Michael Orshansky
2013	J	`jnl`	Probabilistic strain optimization under constraint uncertainty. BMC Syst. Biol. Mona Yousofshahi, Michael Orshansky, Kyongbum Lee, Soha Hassoun
2013	A	`conf`	Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring. ISLPED Tianhao Zheng, Jaeyoung Park, Michael Orshansky, Mattan Erez
2012	J	`jnl`	An accurate sparse-matrix based framework for statistical static timing analysis. Integr. Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Gi-Joon Nam, Michael Orshansky, David Z. Pan
2012	—	`conf`	Embracing local variability to enable a robust high-gain positive-feedback amplifier: Design methodology and implementation. ISQED Kareem Ragab, Ranjit Gharpurey, Michael Orshansky
2012	J	`jnl`	Highly Secure Strong PUF based on Nonlinearity of MOSFET Subthreshold Operation. IACR Cryptol. ePrint Arch. Mukund Kalyanaraman, Michael Orshansky
2012	—	`conf`	Low-energy signal processing using circuit-level timing-error acceptance. ICICDT Ku He, Andreas Gerstlauer, Michael Orshansky
2012	A	`conf`	Modeling and synthesis of quality-energy optimal approximate adders. ICCAD Jin Miao, Ku He, Andreas Gerstlauer, Michael Orshansky
2012	J	`jnl`	Predictable Equation-Based Analog Optimization Based on Explicit Capture of Modeling Error Statistics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ashish Kumar Singh, Kareem Ragab, Mario Lok, Constantine Caramanis, Michael Orshansky
2011	A	`conf`	Controlled timing-error acceptance for low energy IDCT design. DATE Ku He, Andreas Gerstlauer, Michael Orshansky
2011	—	`conf`	Coupling timing objectives with optical proximity correction for improved timing yield. ISQED Shayak Banerjee, Kanak B. Agarwal, Sani R. Nassif, James A. Culp, Lars Liebmann, Michael Orshansky
2010	A	`conf`	A methodology for propagating design tolerances to shape tolerances for use in manufacturing. DATE Shayak Banerjee, Kanak B. Agarwal, Chin Ngai Sze, Sani R. Nassif, Michael Orshansky
2010	A	`conf`	An algorithm for exploiting modeling error statistics to enable robust analog optimization. ICCAD Ashish Kumar Singh, Mario Lok, Kareem Ragab, Constantine Caramanis, Michael Orshansky
2010	—	`conf`	Ground rule slack aware tolerance-driven optical proximity correction for local metal interconnects. CICC Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky
2010	A	`conf`	NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime. ISLPED Mehmet Basoglu, Michael Orshansky, Mattan Erez
2010	A	`conf`	SMATO: Simultaneous mask and target optimization for improving lithographic process window. ICCAD Shayak Banerjee, Kanak B. Agarwal, Michael Orshansky
2009	A	`conf`	Mitigation of intra-array SRAM variability using adaptive voltage architecture. ICCAD Ashish Kumar Singh, Ku He, Constantine Caramanis, Michael Orshansky
2009	J	`jnl`	Statistical analysis of circuit timing using majorization. Commun. ACM Michael Orshansky, Wei-Shen Wang
2008	—	`book`	Design for Manufacturability and Statistical Design - A Constructive Approach. Michael Orshansky, Sani R. Nassif, Duane S. Boning
2008	A	`conf`	Electrically driven optical proximity correction based on linear programming. ICCAD Shayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky
2008	—	`conf`	Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation. ISQED Bin Zhang, Michael Orshansky
2008	J	`jnl`	The Search for Alternative Computational Paradigms. IEEE Des. Test Comput. Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey
2007	J	`jnl`	A Statistical Algorithm for Power- and Timing-Limited Parametric Yield Optimization of Large Integrated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Murari Mani, Anirudh Devgan, Michael Orshansky, Yaping Zhan
2007	—	`conf`	A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions. NANOARCH Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
2007	A*	`conf`	Accurate Waveform Modeling using Singular Value Decomposition with Applications to Timing Analysis. DAC Anand Ramalingam, Ashish Kumar Singh, Sani R. Nassif, Michael Orshansky, David Z. Pan
2007	J	`jnl`	Architecting a reliable CMP switch architecture. ACM Trans. Archit. Code Optim. Kypros Constantinides, Stephen Plaza, Jason A. Blome, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Bin Zhang, Michael Orshansky
2007	—	`conf`	Estimating path delay distribution considering coupling noise. ACM Great Lakes Symposium on VLSI Rajeshwary Tayade, Vijay Kiran Kalyanam, Sani R. Nassif, Michael Orshansky, Jacob A. Abraham
2007	J	`jnl`	Estimation of Leakage Power Consumption and Parametric Yield Based on Realistic Probabilistic Descriptions of Parameters. J. Low Power Electron. Wei-Shen Wang, Michael Orshansky
2007	J	`jnl`	Generation of Efficient Codes for Realizing Boolean Functions in Nanotechnologies CoRR Ashish Kumar Singh, Adnan Aziz, Sriram Vishwanath, Michael Orshansky
2006	A	`conf`	An accurate sparse matrix based framework for statistical static timing analysis. ICCAD Anand Ramalingam, Gi-Joon Nam, Ashish Kumar Singh, Michael Orshansky, Sani R. Nassif, David Z. Pan
2006	J	`jnl`	Analysis of Leakage Power Reduction in Dual-Vth Technologies in the Presence of Large Threshold Voltage Variation. J. Low Power Electron. Wei-Shen Wang, Michael Liu, Michael Orshansky
2006	A	`conf`	Analytical modeling of SRAM dynamic stability. ICCAD Bin Zhang, Ari Arapostathis, Sani R. Nassif, Michael Orshansky
2006	—	`conf`	Application of fast SOCP based statistical sizing in the microprocessor design flow. ACM Great Lakes Symposium on VLSI Murari Mani, Mahesh Sharma, Michael Orshansky
2006	A*	`conf`	BulletProof: a defect-tolerant CMP switch architecture. HPCA Kypros Constantinides, Stephen Plaza, Jason A. Blome, Bin Zhang, Valeria Bertacco, Scott A. Mahlke, Todd M. Austin, Michael Orshansky
2006	—	`conf`	FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs. ISQED Bin Zhang, Wei-Shen Wang, Michael Orshansky
2006	A*	`conf`	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky
2006	Misc	`conf`	Interval-based robust statistical techniques for non-negative convex functions, with application to timing analysis of computer chips. SAC Michael Orshansky, Wei-Shen Wang, Martine Ceberio, Gang Xiang
2006	A	`conf`	Joint design-time and post-silicon minimization of parametric yield loss using adjustable robust optimization. ICCAD Murari Mani, Ashish Kumar Singh, Michael Orshansky
2006	J	`jnl`	Path-Based Statistical Timing Analysis Handling Arbitrary Delay Correlations: Theory and Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei-Shen Wang, Michael Orshansky
2006	A	`conf`	Robust estimation of parametric yield under limited descriptions of uncertainty. ICCAD Wei-Shen Wang, Michael Orshansky
2006	A*	`conf`	Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty. DAC Wei-Shen Wang, Vladik Kreinovich, Michael Orshansky
2006	—	`conf`	Towards formal probabilistic power-performance design space exploration. ACM Great Lakes Symposium on VLSI Joonsoo Kim, Michael Orshansky
2006	—	`conf`	Tutorial II: Variability and Its Impact on Design. ISQED Keith A. Bowman, Michael Orshansky, Sachin S. Sapatnekar
2005	A*	`conf`	An efficient algorithm for statistical minimization of total power under timing yield constraints. DAC Murari Mani, Anirudh Devgan, Michael Orshansky
2005	A	`conf`	Statistical technology mapping for parametric yield. ICCAD Ashish Kumar Singh, Murari Mani, Michael Orshansky
2004	C	`conf`	A New Statistical Optimization Algorithm for Gate Sizing. ICCD Murari Mani, Michael Orshansky
2004	A*	`conf`	Fast statistical timing analysis handling arbitrary delay correlations. DAC Michael Orshansky, Arnab Bandyopadhyay
2004	A	`conf`	Leakage power reduction by dual-vth designs under probabilistic analysis of vth variation. ISLPED Michael Liu, Wei-Shen Wang, Michael Orshansky
2003	A	`conf`	Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. ISLPED David Nguyen, Abhijit Davare, Michael Orshansky, David G. Chinnery, Brandon Thompson, Kurt Keutzer
2002	A*	`conf`	A general probabilistic framework for worst case timing analysis. DAC Michael Orshansky, Kurt Keutzer
2002	—	`conf`	From blind certainty to informed uncertainty. Timing Issues in the Specification and Synthesis of Digital Systems Kurt Keutzer, Michael Orshansky
2002	J	`jnl`	Impact of spatial intrachip gate length variability on theperformance of high-speed digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
2001	J	`jnl`	Efficient generation of pre-silicon MOS model parameters for early circuit design. IEEE J. Solid State Circuits Michael Orshansky, Judy An, Chun Jiang, Bill Liu, Concetta Riccobene, Chenming Hu
2000	A	`conf`	Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits. ICCAD Michael Orshansky, Linda Milor, Pinhong Chen, Kurt Keutzer, Chenming Hu
2000	—	`conf`	New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation. CICC Yu Cao, Takashi Sato, Michael Orshansky, Dennis Sylvester, Chenming Hu
1998	A*	`conf`	A Statistical Performance Simulation Methodology for VLSI Circuits. DAC Michael Orshansky, James C. Chen, Chenming Hu